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81. 发明申请

US20090141787A1 ADAPTIVE EQUALIZATION METHODS AND APPARATUS 有权
标题翻译：自适应均衡方法和装置
公开(公告)号：US20090141787A1
公开(公告)日：2009-06-04
申请号：US12358459
申请日：2009-01-23
申请人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
发明人： Wilson Wong , Sergey Shumarayev , Rakesh Patel
IPC分类号： H04L27/01
CPC分类号： H04L1/205 , H04B17/21 , H04B17/24 , H04B17/309 , H04L25/03006
摘要： A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.
摘要翻译：系统包括经由用于从发射机向接收机发送高速数据信号的传输介质连接到可编程接收机设备（例如，另一个PLD）的可编程发射机设备（例如，PLD）。在测试操作模式期间，发射机和接收机之间的低速通信链路允许这些设备一起工作，以经由传输介质从发射机向接收机发送具有已知特性的测试信号，以分析由接收器，并且至少部分地补偿由接收器接收的测试信号中的损耗，系统的至少一些方面（例如，接收机中的均衡器电路）。

82. 发明授权

US07397270B1 Dynamically-adjustable differential output drivers 有权
标题翻译：动态可调差分输出驱动器
公开(公告)号：US07397270B1
公开(公告)日：2008-07-08
申请号：US11138919
申请日：2005-05-25
申请人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
发明人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/00369 , H03K19/01812 , H03K19/01837 , H03K19/018514 , H03K19/018585
摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
摘要翻译：使用动态可调差分输出驱动器提供系统和方法。诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。可以调整输出驱动器的峰峰值输出电压和共模电压。动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

83. 发明申请

US20070188353A1 DYNAMIC BIAS CIRCUIT 有权
标题翻译：动态偏置电路
公开(公告)号：US20070188353A1
公开(公告)日：2007-08-16
申请号：US11735113
申请日：2007-04-13
申请人： Tin Lai , Wilson Wong , Sergey Shumarayev
发明人： Tin Lai , Wilson Wong , Sergey Shumarayev
IPC分类号： H03M7/00
CPC分类号： G11C7/12 , G11C7/1045 , H03M1/662
摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.
摘要翻译：偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D 2A）。 D 2 A耦合到作为形成数据链的多个寄存器帧之一的主寄存器帧。多个寄存器帧被串行链接，数据链内的数据在多个寄存器帧之间移位。通过时域复用方案，D 2 A可由均衡电路的控制旋钮共享。偏置电路包括还耦合到主寄存器框架的解码器。还包括一个输出使能逻辑模块。当数据链中的数据根据时钟周期进行移位时，输出使能逻辑模块确定主寄存器何时具有完整的数据集。还提供了一种通过偏置电路调整信号的方法。

84. 发明申请

US20070147478A1 Signal adjustment receiver circuitry 有权
标题翻译：信号调节接收器电路
公开(公告)号：US20070147478A1
公开(公告)日：2007-06-28
申请号：US11486581
申请日：2006-07-14
申请人： Tin Lai , Wilson Wong , Sergey Shumarayev , Simardeep Maangat
发明人： Tin Lai , Wilson Wong , Sergey Shumarayev , Simardeep Maangat
IPC分类号： H04B1/00
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies. For low frequency adjustment, user-programmable parameters control the normalized signal amplitude in the signal normalization block and the low frequency adjustment in the equalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频的均衡块中的频率调整。对于低频调整，用户可编程参数控制信号归一化块中的归一化信号幅度和均衡块中的低频调整。

85. 发明申请

US20070140387A1 Signal adjustment receiver circuitry 有权
标题翻译：信号调节接收器电路
公开(公告)号：US20070140387A1
公开(公告)日：2007-06-21
申请号：US11312181
申请日：2005-12-20
申请人： Wilson Wong , Rakesh Patel , Sergey Shumarayev , Tin Lai
发明人： Wilson Wong , Rakesh Patel , Sergey Shumarayev , Tin Lai
IPC分类号： H04L27/06
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。对于低频调整，控制块控制信号归一化块中的归一化信号幅度。以这种方式，在信号归一化块中执行低频内容的受控调整。

86. 发明申请

US20070041455A1 High-speed serial data receiver architecture 有权
标题翻译：高速串行数据接收机架构
公开(公告)号：US20070041455A1
公开(公告)日：2007-02-22
申请号：US11361192
申请日：2006-02-23
申请人： Thungoc Tran , Sergey Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
发明人： Thungoc Tran , Sergey Shumarayev , Simardeep Maangat , Wilson Wong , Rakesh Patel
IPC分类号： H04L25/00
CPC分类号： H04L1/243 , H04L25/03878
摘要： Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.
摘要翻译：用于包含在PLD中的串行数据信号接收器电路包括串联连接并且可单独控制的多个均衡器电路，使得它们可以统一地补偿宽范围的可能的输入信号衰减特性。其他电路特征可以相对于均衡器电路连接以给予接收机电路其他能力。例如，这些其他特征可以包括各种类型的环回测试电路，可控终端电阻，可控共模电压以及用于检测输入信号的可控阈值。接收器电路的控制的各个方面可以是可编程的。

87. 发明授权

US07135885B2 Dynamically adjustable signal detector 有权
标题翻译：动态可调信号检测器
公开(公告)号：US07135885B2
公开(公告)日：2006-11-14
申请号：US11270229
申请日：2005-11-08
申请人： Wilson Wong , Sergey Shumarayev
发明人： Wilson Wong , Sergey Shumarayev
IPC分类号： H03K19/03
CPC分类号： G01R31/31932 , G01R31/3167 , H03K5/1252 , H03K19/003 , H04L25/0292
摘要： A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.
摘要翻译：动态可调信号检测器接收差分输入信号，并且基于动态可调的阈值设置输出表示是否正在接收有效信号的信号。阈值设置可以包括差分电压，峰值功率，平均功率或其他适当的设置，并且可以为所选阈值设置具有动态可调整的值。可以使用由可编程逻辑资源电路设置的控制信号，通过编程到可编程逻辑资源中的软知识产权，由处理器，可编程逻辑资源外部的电路设置阈值设置和值，或用户输入。

88. 发明申请

US20060165204A1 Method and apparatus for multi-mode clock data recovery 失效
公开(公告)号：US20060165204A1
公开(公告)日：2006-07-27
申请号：US11040342
申请日：2005-01-21
申请人： Sergey Shumarayev , Rakesh Patel , Wilson Wong , Tim Hoang
发明人： Sergey Shumarayev , Rakesh Patel , Wilson Wong , Tim Hoang
IPC分类号： H04L7/00 , H03D3/24
CPC分类号： H03L7/0998 , H03L7/081 , H03L7/087 , H03L7/113 , H03L7/14 , H04L7/0025 , H04L7/0083 , H04L7/033
摘要： The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.

89. 发明申请

US20060066347A1 Dynamically adjustable signal detector 有权
公开(公告)号：US20060066347A1
公开(公告)日：2006-03-30
申请号：US11270229
申请日：2005-11-08
申请人： Wilson Wong , Sergey Shumarayev
发明人： Wilson Wong , Sergey Shumarayev
IPC分类号： H03K19/003
CPC分类号： G01R31/31932 , G01R31/3167 , H03K5/1252 , H03K19/003 , H04L25/0292
摘要： A dynamically adjustable signal detector receives a differential input signal and outputs a signal indicative of whether a valid signal is being received based on dynamically adjustable threshold settings. The threshold settings can include differential voltage, peak power, average power, or other suitable settings, and can have a dynamically adjustable value for a selected threshold setting. The threshold settings and the value for a selected threshold setting can be set using control signals that are set by programmable logic resource circuitry, by soft intellectual property programmed into a programmable logic resource, by a processor, by circuitry external to a programmable logic resource, or by user input.

90. 发明申请

US20050237082A1 Integrated circuit output driver circuitry with programmable preemphasis 有权
公开(公告)号：US20050237082A1
公开(公告)日：2005-10-27
申请号：US11148046
申请日：2005-06-07
申请人： Sergey Shumarayev , Thomas White , Rakesh Patel , Wilson Wong
发明人： Sergey Shumarayev , Thomas White , Rakesh Patel , Wilson Wong
IPC分类号： H03K19/0185 , H03K19/177 , H04L25/02 , H03K19/003
CPC分类号： H03K19/17744 , H03K19/018585 , H03K19/1778 , H04L25/0272 , H04L25/0286
摘要： Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

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