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1. 发明授权

US11714128B2 Method and apparatus for testing artificial intelligence chip, device and storage medium 有权
公开(公告)号：US11714128B2
公开(公告)日：2023-08-01
申请号：US17021080
申请日：2020-09-15
申请人： KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITED
发明人： Ziyu Guo
IPC分类号： G01R31/3177 , G06N5/02 , G01R31/3185 , G01R31/317 , G06F115/08 , G06F11/22 , G01R31/3193 , G01R31/319
CPC分类号： G01R31/3177 , G06N5/02 , G01R31/3193 , G01R31/31701 , G01R31/31703 , G01R31/31704 , G01R31/31912 , G01R31/31932 , G01R31/318519 , G01R31/318583 , G06F11/2226 , G06F11/2236 , G06F2115/08
摘要： The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

2. 发明申请

US20180164370A1 GENERIC WIDTH INDEPENDENT PARALLEL CHECKER FOR A DEVICE UNDER TEST 审中-公开
公开(公告)号：US20180164370A1
公开(公告)日：2018-06-14
申请号：US15375542
申请日：2016-12-12
申请人： STMicroelectronics International N.V.
发明人： Tejinder Kumar , Suchi Prabhu Tandel , Rakesh Malik
IPC分类号： G01R31/317 , G01R31/3193
CPC分类号： G01R31/31703 , G01R31/3171 , G01R31/31932 , G01R31/31935 , G11C15/00 , G11C29/36 , G11C29/38 , G11C29/44 , G11C2029/0405 , G11C2029/2602
摘要： Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

3. 发明申请

US20180052205A1 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING THRESHOLD VOLTAGE MEASUREMENT CIRCUITRY 审中-公开
公开(公告)号：US20180052205A1
公开(公告)日：2018-02-22
申请号：US15678658
申请日：2017-08-16
申请人： ATOMERA INCORPORATED
发明人： Richard Stephen ROY
IPC分类号： G01R31/319 , H01L27/108 , H01L21/66 , H01L29/10 , H01L29/15 , H01L29/16 , G11C11/4078 , G01R31/26 , G01R31/3193
CPC分类号： G01R31/2831 , G01R31/2644 , G01R31/2648 , G01R31/275 , G01R31/2894 , G01R31/31924 , G01R31/31932 , G11C11/4078 , G11C11/4087 , G11C29/50004 , H01L21/823412 , H01L22/34 , H01L27/092 , H01L27/10897 , H01L29/105 , H01L29/152 , H01L29/16 , H01L29/7843 , H01L29/7849 , H03F3/45183 , H03F2200/453 , H03F2203/45361 , H03F2203/45368
摘要： A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice.

4. 发明授权

US09222977B2 Semiconductor test system and method 有权
标题翻译：半导体测试系统及方法
公开(公告)号：US09222977B2
公开(公告)日：2015-12-29
申请号：US14807214
申请日：2015-07-23
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/26 , G01R31/3177 , G01R31/3185 , G01R31/317 , G01R31/3193 , G06F11/26 , G06F11/277 , G01R31/319
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318566 , G01R31/318572 , G01R31/31926 , G01R31/31932 , G06F11/26 , G06F11/277
摘要： A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
摘要翻译：测试控制器将测试激励信号并行地施加到晶片上的多个管芯的输入焊盘。测试控制器还将编码的测试响应信号并行地应用于多个管芯的输出焊盘。编码的测试响应信号在芯片上解码，并与通过将测试激励信号应用于芯片上的核心电路产生的核心测试响应信号进行比较。该比较产生加载到IEEE 1149.1扫描路径的扫描单元中的通过/失败信号。然后可以将通过/失败信号扫描出模具以确定测试结果。

5. 发明授权

US09151801B2 Measurement circuit and test apparatus 有权
标题翻译：测量电路和测试仪器
公开(公告)号：US09151801B2
公开(公告)日：2015-10-06
申请号：US13165796
申请日：2011-06-22
申请人： Masahiro Ishida , Kiyotaka Ichiyama
发明人： Masahiro Ishida , Kiyotaka Ichiyama
IPC分类号： G01R31/319 , G01R31/3193 , G01R31/317
CPC分类号： G01R31/31932 , G01R31/31703 , G01R31/31924
摘要： Provided is a measurement circuit that measures a signal under measurement input thereto, comprising a level comparing section that outputs a logic value according to a comparison result between a signal level of the signal under measurement and a set threshold level; a logic comparing section that acquires the logic value output by the level comparing section at a comparison timing input thereto; and a timing adjusting section that adjusts relative phases of a signal output by the level comparing section and the comparison timing, based on the expected value pattern of the signal under measurement and the threshold level.
摘要翻译：提供一种测量输入信号的测量电路，包括：电平比较部分，根据测量信号的信号电平与设定的阈值电平之间的比较结果输出逻辑值; 逻辑比较部，其在输入的比较定时获取由所述电平比较部输出的逻辑值; 以及定时调整部，其基于所测量的信号的期望值模式和阈值水平，调整由所述电平比较部输出的信号和所述比较定时的相对相位。

6. 发明申请

US20150128003A1 AUTOMATED TEST SYSTEM WITH EVENT DETECTION CAPABILITY 有权
标题翻译：具有事件检测能力的自动测试系统
公开(公告)号：US20150128003A1
公开(公告)日：2015-05-07
申请号：US14073739
申请日：2013-11-06
申请人： Ronald A. Sartschev , Edward J. Seng , Marc Reuben Hutner
发明人： Ronald A. Sartschev , Edward J. Seng , Marc Reuben Hutner
IPC分类号： G01R31/319
CPC分类号： G01R31/31922 , G01R31/31703 , G01R31/31722 , G01R31/31727 , G01R31/318594 , G01R31/31917 , G01R31/31928 , G01R31/31932 , H04L1/242 , H04L27/0008 , H04L27/2053 , H04L27/22 , H04L27/38
摘要： A test technique that may be implemented in an automated test system for testing semiconductor devices. The test technique may enable the fast detection of a signal transition, such as an edge, within a waveform and the timing of that event. Circuitry within a digital instrument that can be quickly and flexibly programmed may, at least in part, implement the test technique. That circuitry may be simply programmed with testing parameters, such that application of the technique may lead to faster test development and faster times. In operation, that circuitry receives parameters specifying parameters of a window over a waveform in which samples of the waveform will be taken to detect the signal transition. The circuitry may convert these parameters into control signals for other components in the test system, such as an edge generator or pin electronics, to take a programmed number of samples at desired times.
摘要翻译：可以在用于测试半导体器件的自动化测试系统中实现的测试技术。测试技术可以使得能够快速检测波形内的信号转换（例如边沿）以及该事件的定时。可以快速灵活地编程的数字仪器内的电路可以至少部分地实现测试技术。该电路可以简单地用测试参数编程，使得该技术的应用可以导致更快的测试开发和更快的时间。在操作中，该电路接收指定波形的参数的参数，其中将采取波形的采样来检测信号转换。电路可以将这些参数转换成测试系统中的其他部件（例如边缘发生器或引脚电子器件）的控制信号，以在期望的时间取得编程的样本数量。

7. 发明申请

US20150074094A1 COMPARISON DEVICE AND METHOD FOR COMPARING TEST PATTERN FILES OF A WAFER TESTER 有权
标题翻译：比较测试仪的测试图案的比较装置和方法
公开(公告)号：US20150074094A1
公开(公告)日：2015-03-12
申请号：US14543167
申请日：2014-11-17
申请人： King Yuan Electronics Co., Ltd.
发明人： Fu-Tai CHEN
IPC分类号： G06F17/30
CPC分类号： G01R31/318342 , G01R31/31932
摘要： A comparison device for comparing test pattern files of a wafer tester includes a storage unit and a processing unit. The comparison device stores a first to-be-compared file and a second to-be-compared file into the storage unit. The processing unit reads the first to-be-compared file and the second to-be-compared file from the storage unit to process and executes comparison operation, so as to generate a comparison result. The comparison operation compares the words in a first section of the first to-be-compared file with the words in a second section of the second to-be-compared file in a one-to-one manner, wherein, if the first section ending point is not the end of the first to-be-compared file or the second section ending point is not the end of the second to-be-compared file, the processing unit resets the first section and the second section, and executes comparison operation again.
摘要翻译：用于比较晶片测试仪的测试图案文件的比较装置包括存储单元和处理单元。比较装置将第一待比较文件和第二待比较文件存储到存储单元中。处理单元从存储单元读取第一待比较文件和第二待比较文件，以处理并执行比较操作，以便生成比较结果。比较操作将第一待比较文件的第一部分中的单词与第二待比较文件的第二部分中的单词以一对一的方式进行比较，其中如果第一部分结束点不是第一待比较文件的结束，或者第二部分结束点不是第二待比较文件的结束，处理单元复位第一部分和第二部分，并且执行比较再次运作

8. 发明申请

US20140181609A1 SEMICONDUCTOR TEST SYSTEM AND METHOD 有权
公开(公告)号：US20140181609A1
公开(公告)日：2014-06-26
申请号：US14191964
申请日：2014-02-27
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318566 , G01R31/318572 , G01R31/31926 , G01R31/31932 , G06F11/26 , G06F11/277
摘要： A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

9. 发明申请

US20140043051A1 INSPECTION APPARATUS, INSPECTION SYSTEM AND INSPECTION METHOD 审中-公开
标题翻译：检验仪器，检验系统和检验方法
公开(公告)号：US20140043051A1
公开(公告)日：2014-02-13
申请号：US14051582
申请日：2013-10-11
申请人： TOKYO ELECTRON LIMITED
发明人： Haruo IWATSU , Yoshinori FUJISAWA
IPC分类号： G01R31/319
CPC分类号： G01R31/31919 , G01R31/2889 , G01R31/31932 , G01R31/31935 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： An inspection apparatus for inspecting target objects includes multiple inspection cells corresponding to target objects, respectively, and a test-pattern wiring formed between the inspection cells. Each of the inspection cell includes a test pattern memory device which temporarily stores a test pattern, an inspection signal driver device which transmits an inspection signal to a respective one of the target objects based on the test pattern, a comparator device which compares an output signal from the respective one of the target objects with an expected value corresponding to the test pattern such that a test result is obtained, and a test result memory device which temporarily stores the test result, and the test-pattern wiring transmits the test pattern to the test pattern memory device of each of the inspection cells from an upstream side to a downstream side in the order that the target objects are inspected.
摘要翻译：用于检查目标物体的检查装置分别包括对应于目标物体的多个检查单元和形成在检查单元之间的测试图案布线。每个检查单元包括临时存储测试图案的测试图案存储器件，基于测试图案将检查信号发送到相应的一个目标对象的检查信号驱动器设备，比较器设备，其将输出信号从相应的一个目标对象获得具有与测试图案相对应的期望值以获得测试结果，以及临时存储测试结果的测试结果存储设备，并且测试图案布线将测试图案发送到每个检查单元的测试图案存储装置按照目标对象被检查的顺序从上游侧到下游侧。

10. 发明授权

US08607109B2 Test circuitry including core output, expected response, and mask circuitry 有权
标题翻译：测试电路包括核心输出，预期响应和掩码电路
公开(公告)号：US08607109B2
公开(公告)日：2013-12-10
申请号：US13909384
申请日：2013-06-04
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/3177 , G01R31/31703 , G01R31/318511 , G01R31/318533 , G01R31/318536 , G01R31/318541 , G01R31/318544 , G01R31/318566 , G01R31/318572 , G01R31/31926 , G01R31/31932 , G06F11/26 , G06F11/277
摘要： A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
摘要翻译：测试控制器将测试激励信号并行地施加到晶片上的多个管芯的输入焊盘。测试控制器还将编码的测试响应信号并行地应用于多个管芯的输出焊盘。编码的测试响应信号在芯片上解码，并与通过将测试激励信号应用于芯片上的核心电路产生的核心测试响应信号进行比较。该比较产生加载到IEEE 1149.1扫描路径的扫描单元中的通过/失败信号。然后可以将通过/失败信号扫描出模具以确定测试结果。

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