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81. 发明授权

US09697874B1 Monolithic memory comprising 1T1R code memory and 1TnR storage class memory 有权
公开(公告)号：US09697874B1
公开(公告)日：2017-07-04
申请号：US15178144
申请日：2016-06-09
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari , Sundar Narayanan
IPC分类号： G11C5/12 , G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C5/12 , G11C5/025 , G11C5/063 , G11C11/1659 , G11C13/0007 , G11C13/003 , G11C2213/78 , G11C2213/79 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/16
摘要： Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.

82. 发明授权

US09685608B2 Reduced diffusion in metal electrode for two-terminal memory 有权
公开(公告)号：US09685608B2
公开(公告)日：2017-06-20
申请号：US14207430
申请日：2014-03-12
申请人： Crossbar, Inc.
发明人： Steven Patrick Maxwell , Sung Hyun Jo
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： H01L45/1266 , G11C13/0002 , G11C13/0011 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/77 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/16
摘要： Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

83. 发明授权

US09659642B1 State change detection for two-terminal memory during application of a state-changing stimulus 有权
公开(公告)号：US09659642B1
公开(公告)日：2017-05-23
申请号：US14983649
申请日：2015-12-30
申请人： Crossbar, Inc.
发明人： Sang Nguyen , Cung Vu , Dzung Huu Nguyen , Hagop Nazarian , John Nguyen , Tianhong Yan
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0064 , G11C13/0097 , G11C2013/0054 , G11C2013/0066 , G11C2013/009 , G11C2213/79
摘要： A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state (e.g., to a highest resistance state), but existing techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that causes the state change.

84. 发明授权

US09633724B2 Sensing a non-volatile memory device utilizing selector device holding characteristics 有权
公开(公告)号：US09633724B2
公开(公告)日：2017-04-25
申请号：US14755998
申请日：2015-06-30
申请人： Crossbar, Inc.
发明人： Sung Hyun Jo , Hagop Nazarian , Lin Shih Liu
IPC分类号： G11C13/00 , G11C14/00 , G11C11/16 , G11C29/02
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C13/003 , G11C13/0033 , G11C13/0061 , G11C14/00 , G11C14/0045 , G11C29/026 , G11C29/028 , G11C2013/0071 , G11C2213/51 , G11C2213/73 , G11C2213/76
摘要： Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

85. 发明授权

US09627443B2 Three-dimensional oblique two-terminal memory with enhanced electric field 有权
公开(公告)号：US09627443B2
公开(公告)日：2017-04-18
申请号：US14194499
申请日：2014-02-28
申请人： Crossbar, Inc.
发明人： Sung Hyun Jo , Joanna Bettinger , Xianliang Liu
IPC分类号： H01L27/115 , H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/249 , G11C13/0007 , G11C13/0011 , G11C2213/50 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2418 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/145 , H01L45/146 , H01L45/148
摘要： Providing for three-dimensional memory cells having enhanced electric field characteristics is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

86. 发明授权

US09590013B2 Device switching using layered device structure 有权
标题翻译：使用分层设备结构的设备切换
公开(公告)号：US09590013B2
公开(公告)日：2017-03-07
申请号：US14509967
申请日：2014-10-08
申请人： Crossbar, Inc.
发明人： Sung Hyun Jo , Wei Lu
IPC分类号： H01L45/00 , H01L27/24 , G11C13/00 , H04L12/721
CPC分类号： H01L27/2436 , G11C13/0009 , G11C2213/15 , G11C2213/33 , G11C2213/51 , H01L27/2463 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/148 , H01L45/16 , H01L45/1608 , H04L45/12
摘要： A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.
摘要翻译：电阻式开关装置。该器件包括第一电极，其包括覆盖第一电介质材料的第一金属材料和包含非晶硅材料的开关材料。该装置包括包括至少第二金属材料的第二电极。在具体实施例中，该装置包括设置在第一电极和开关材料之间的缓冲材料。缓冲材料在开关材料和第一电极之间提供阻挡区域，使得当向第二电极施加第一电压时，阻挡区域基本上不含有来自第二金属材料的金属颗粒。

87. 发明授权

US09520561B1 Controlling on-state current for two-terminal memory 有权
公开(公告)号：US09520561B1
公开(公告)日：2016-12-13
申请号：US14798074
申请日：2015-07-13
申请人： Crossbar, Inc.
发明人： Kuk-Hwan Kim , Ping Lu , Chen-Chun Chen , Sung Hyun Jo
IPC分类号： H01L47/00 , H01L29/04 , H01L21/00 , H01L21/20 , H01L45/00
CPC分类号： H01L45/1608 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148
摘要： Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.

88. 发明授权

US09489997B2 Hardware assisted meta data lookup 有权
标题翻译：硬件辅助元数据查询
公开(公告)号：US09489997B2
公开(公告)日：2016-11-08
申请号：US13935390
申请日：2013-07-03
申请人： Crossbar, Inc.
发明人： Frank Edelhaeuser
IPC分类号： G06F12/00 , G11C11/00 , G11C13/00 , G11C15/04 , G06F12/10
CPC分类号： G11C11/005 , G11C13/0002 , G11C15/04 , G11C15/046 , G11C2213/71 , G11C2213/77
摘要： A memory system including a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing metadata. A compare circuit is configured to receive metadata retrieved from a plurality of pages sequentially and compare the retrieved metadata to a search pattern. The physical location of the page can be determined by finding the search pattern. The memory array and the compare circuit are formed in different layers of the substrate.
摘要翻译：一种包括存储器件的存储器系统。存储器件包括衬底。存储器阵列定义多个页面，每个页面包括用于存储数据的数据区域和用于存储元数据的备用区域。比较电路被配置为顺序地接收从多个页面检索的元数据，并将所检索的元数据与搜索模式进行比较。可以通过查找搜索模式来确定页面的物理位置。存储器阵列和比较电路形成在衬底的不同层中。

89. 发明授权

US09437814B1 Mitigating damage from a chemical mechanical planarization process 有权
标题翻译：减轻化学机械平面化过程造成的损害
公开(公告)号：US09437814B1
公开(公告)日：2016-09-06
申请号：US14473879
申请日：2014-08-29
申请人： Crossbar, Inc.
发明人： Harry Yue Gee , Majid Milani , Natividad Vasquez, Jr. , Steven Patrick Maxwell , Sundar Narayanan
IPC分类号： H01L21/332 , H01L45/00
CPC分类号： H01L45/16 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/145
摘要： During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.
摘要翻译：在制造双端存储器件期间，可以形成端子（例如，底端）。在端子形成之后，可以应用化学机械平面化（CMP）工艺，根据端子的组成，可以引起影响成品存储器件或电池的工作特性的损坏。在一些实施例中，可以通过一个或多个后CMP工艺来去除这种损伤。在一些实施例中，可以减轻这种损害，以便防止在完成CMP过程之前通过例如在端子顶部形成牺牲层来完全发生损坏。因此，牺牲层可以操作以保护端子免受由CMP工艺引起的损伤，在完成两端存储器件的制造之前牺牲层的其余部分被去除。

90. 发明授权

US09397291B1 RRAM with dual mode operation 有权
公开(公告)号：US09397291B1
公开(公告)日：2016-07-19
申请号：US14802477
申请日：2015-07-17
申请人： Crossbar, Inc.
发明人： Sung Hyun Jo
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/145 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C13/0097 , G11C13/04 , G11C2013/0073 , G11C2213/15 , G11C2213/55 , G11C2213/77 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/16
摘要： A two-terminal memory cell comprises a dual mode of operation in a unipolar mode and bipolar mode for a programming or On-state and for an erase or Off-state of the cell. The two-terminal memory cell is field programmable and can be flexibly designed or integrated into existing architecture. The two-terminal memory comprises a first electrode layer and a second electrode layer with a switching layer disposed between that has an electrical insulator material. A semiconductor layer is disposed between the switching layer and at least one of the first electrode or the second electrode. The switching layer generates a conductive path that is configured to be in a program state and an erase state, based on a bipolar mode and a unipolar mode.

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