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81. 发明授权

US09251891B1 Devices and methods to conditionally send parameter values to non-volatile memory 有权
标题翻译：有条件地将参数值发送到非易失性存储器的设备和方法
公开(公告)号：US09251891B1
公开(公告)日：2016-02-02
申请号：US14538128
申请日：2014-11-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： Ken Jianhui Hu , Nian Niles Yang , Bhuvan Khurana , Lee M. Gavens , Kulachet Tanpairoj
IPC分类号： G11C16/04 , G11C11/56 , G11C16/10 , G11C16/26
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C2211/5641
摘要： A data storage device that includes a controller and a non-volatile memory may perform a method that includes comparing, in the controller, first parameter values of a first group of parameter values to second parameter values of a second group of parameter values. The second parameter values of the second group of parameter values are associated with a scheduled non-volatile memory operation. The first parameter values correspond to parameter values that are in the non-volatile memory. The method includes sending, from the controller to the non-volatile memory, a parameter value of the second group in response to determining that the parameter value differs from a corresponding parameter value of the first group.
摘要翻译：包括控制器和非易失性存储器的数据存储设备可以执行一种方法，其包括在控制器中比较第一组参数值的第一参数值与第二组参数值的第二参数值。第二组参数值的第二参数值与调度的非易失性存储器操作相关联。第一个参数值对应于非易失性存储器中的参数值。该方法包括响应于确定参数值与第一组的对应参数值不同，从控制器向非易失性存储器发送第二组的参数值。

82. 发明授权

US09246511B2 Method and apparatus to process data based upon estimated compressibility of the data 有权
标题翻译：基于估计的数据压缩性来处理数据的方法和装置
公开(公告)号：US09246511B2
公开(公告)日：2016-01-26
申请号：US13425016
申请日：2012-03-20
申请人： Alon Kipnis , Itai Dror
发明人： Alon Kipnis , Itai Dror
IPC分类号： G06F3/00 , H03M7/30 , H04L29/06
CPC分类号： H03M7/30 , H03M7/3071 , H03M7/3079 , H04L69/04
摘要： A method includes, in a data storage device, determining an estimated compression ratio. The estimated compression ratio is based on hash values of a subset of a data set. The method includes selectively processing the data set based on the estimated compression ratio prior to storage of data associated with the data set in a memory of the data storage device.
摘要翻译：一种方法包括在数据存储装置中确定估计的压缩比。估计压缩比基于数据集的子集的哈希值。该方法包括在存储与数据存储设备的存储器中的数据集相关联的数据之前，基于估计的压缩比来选择性地处理数据集。

83. 发明授权

US09245637B2 Systems and methods for read disturb management in non-volatile memory 有权
标题翻译：非易失性存储器中读取干扰管理的系统和方法
公开(公告)号：US09245637B2
公开(公告)日：2016-01-26
申请号：US14020634
申请日：2013-09-06
申请人： SanDisk Technologies Inc.
发明人： Nian Niles Yang , Chris Avila , Steven Sprouse , Alexandra Bauche
IPC分类号： G11C16/06 , G11C16/26 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3427 , G11C16/3459
摘要： Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.
摘要翻译：非易失性存储器和读取非易失性存储器的方法被提供用于管理和减少读取相关的干扰。引入技术以在读取操作期间使用状态依赖的读通道电压来减少特定字线的读取干扰。由于它们靠近所选择的字线，所以可以使用状态相关的通过电压来偏置相邻字线，而使用标准或第二组通过电压来偏置其它未选字线。通常，施加到与所选字线相邻的字线的每个状态依赖的通过电压大于施加到其他未选择的字线的第二组通过电压，尽管这不是必需的。其他字线也可能使用状态依赖的通过电压偏置。系统级技术提供或独立于状态依赖的通过电压，以进一步减少和管理读取干扰。技术可以解释数据有效性和存储器写入和擦除周期。

84. 发明授权

US09244631B2 Lower page only host burst writes 有权
公开(公告)号：US09244631B2
公开(公告)日：2016-01-26
申请号：US14099027
申请日：2013-12-06
申请人： SanDisk Technologies Inc.
发明人： Sergey Gorobets , Chris Avila , Steven T. Sprouse
IPC分类号： G06F12/00 , G06F3/06 , G06F12/06 , G06F12/02
CPC分类号： G06F3/0688 , G06F3/061 , G06F3/0616 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F12/0646 , G06F2212/7207 , G06F2212/7208
摘要： In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

85. 发明授权

US09240238B2 Back gate operation with elevated threshold voltage 有权
标题翻译：后门操作提升阈值电压
公开(公告)号：US09240238B2
公开(公告)日：2016-01-19
申请号：US14033100
申请日：2013-09-20
申请人： SanDisk Technologies Inc.
发明人： Deepak Raghu , Gautam Dusija , Chris Avila , Yingda Dong , Man Mui
IPC分类号： G11C16/04 , G11C16/10 , G11C11/56 , G11C16/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3427
摘要： In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor threshold voltages cannot be returned to a desired threshold voltage range then modified program conditions, including increased back gate voltage, may be used to allow programming.
摘要翻译：在三维NAND存储器中，背栅晶体管中增加的阈值电压可能导致程序故障，特别是在靠近后门的字线上。当背栅极晶体管阈值电压不能返回到期望的阈值电压范围时，可以使用包括增加的背栅电压的修改的程序条件来允许编程。

86. 发明授权

US09239610B2 Systems and methods for managing data in a system for hibernation states 有权
标题翻译：用于管理休眠状态的系统中的数据的系统和方法
公开(公告)号：US09239610B2
公开(公告)日：2016-01-19
申请号：US13780834
申请日：2013-02-28
申请人： Yair Baram , Hanan Borukhov , Idan Alrod , Eran Sharon
发明人： Yair Baram , Hanan Borukhov , Idan Alrod , Eran Sharon
IPC分类号： G06F1/00 , G06F1/32 , G06F1/26
CPC分类号： G06F1/3275 , G06F1/26 , G06F1/3206 , G06F1/3246 , Y02D10/13 , Y02D10/14
摘要： The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor. The processor is configured to manage data storage in conjunction with hibernation of the memory device. The processor is in communication with the controller memory, the main memory and the buffer, and is configured to read data from the controller memory; write at least a portion of the data read from the controller memory into the buffer prior to the memory device entering a hibernation state; and after writing the at least a portion of the data read from the controller memory into the buffer and prior to the memory device entering the hibernation state, reduce an amount of power provided to the buffer of the to a reduced power level.
摘要翻译：本申请涉及用于管理用于休眠状态的系统中的数据的系统和方法。在一个实现中，存储器件包括控制器存储器，主存储器，到主存储器的缓冲器和包括处理器的控制器。处理器被配置为结合存储器设备的休眠来管理数据存储。处理器与控制器存储器，主存储器和缓冲器通信，并被配置为从控制器存储器读取数据; 在存储器件进入休眠状态之前将从控制器存储器读取的数据的至少一部分写入缓冲器; 并且在将从控制器存储器读取的数据的至少一部分写入缓冲器之后并且在存储器件进入休眠状态之前，将提供给缓冲器的功率量减少到降低的功率电平。

87. 发明申请

US20160011790A1 SYSTEMS AND METHODS TO ENABLE ACCESS TO A HOST MEMORY ASSOCIATED WITH A UNIFIED MEMORY ARCHITECTURE (UMA) 审中-公开
标题翻译：能够访问与统一存储器架构（UMA）相关的主机存储器的系统和方法
公开(公告)号：US20160011790A1
公开(公告)日：2016-01-14
申请号：US14330552
申请日：2014-07-14
申请人： SANDISK TECHNOLOGIES INC.
发明人： TAL ROSTOKER , ALON MARCU , ROTEM SELA
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0679 , G06F12/0862 , G06F12/0868 , G06F13/1668 , G06F13/28 , G06F2212/1024 , G06F2212/214 , G06F2212/311 , G06F2212/6024
摘要： A method includes, in a data storage device including a non-volatile memory, receiving, from a host device, a read command to read data from the non-volatile memory. The host device is coupled to the data storage device and includes a memory having a unified memory (UM) area. The method also includes, responsive to the read command, sending a UM read command to the host device. The UM read command instructs the host device to read the data from a location of the UM area.
摘要翻译：一种方法包括在包括非易失性存储器的数据存储设备中从主机设备接收读取命令以从非易失性存储器读取数据。主机设备耦合到数据存储设备并且包括具有统一存储器（UM）区域的存储器。该方法还包括响应于读取命令向主机设备发送UM读取命令。 UM读取命令指示主机设备从UM区域的位置读取数据。

88. 发明授权

US09236393B1 3D NAND memory with socketed floating gate cells 有权
标题翻译：具有插座浮动栅极的3D NAND存储器
公开(公告)号：US09236393B1
公开(公告)日：2016-01-12
申请号：US14494869
申请日：2014-09-24
申请人： SanDisk Technologies, Inc.
发明人： Raul Adrian Cernea
IPC分类号： H01L27/115 , H01L29/423 , H01L29/788 , H01L29/04
CPC分类号： H01L27/11556 , G11C11/5671 , G11C16/0483 , H01L27/11524 , H01L27/11551 , H01L29/04 , H01L29/42324 , H01L29/788 , H01L29/7883
摘要： A 3D NAND memory has vertical NAND strings across multiple memory planes above a substrate, with each memory cell of a NAND string residing in a different memory layer. Word lines in each memory plane each has a series of socket components aligned to embed respective floating gates of a group memory cells. In this way, the word line to floating gate capacitive coupling is enhanced thereby allowing a 4 to 8 times reduction in cell dimension as well as reducing floating-gate perturbations between neighboring cells. In one embodiment, each NAND string has source and drain switches that each employs an elongated polysilicon gate with metal strapping to enhance switching. The memory is fabricated by an open-trench process on a multi-layer slab that creates lateral grottoes for forming the socket components.
摘要翻译： 3D NAND存储器具有跨越衬底上的多个存储器平面的垂直NAND串，NAND串的每个存储单元驻留在不同的存储器层中。每个存储器平面中的字线各自具有一系列插座组件，其对齐以嵌入组存储器单元的相应浮动栅极。以这种方式，增加了对浮栅电容耦合的字线，从而允许单元尺寸减小4至8倍以及减少相邻单元之间的浮栅扰动。在一个实施例中，每个NAND串具有源极和漏极开关，其各自采用具有金属带的细长多晶硅栅极以增强切换。存储器是通过多层板上的开沟工艺制造的，其形成用于形成插座部件的侧向洞穴。

89. 发明授权

US09236128B1 Voltage kick to non-selected word line during programming 有权
标题翻译：在编程期间电压踢到未选择的字线
公开(公告)号：US09236128B1
公开(公告)日：2016-01-12
申请号：US14612010
申请日：2015-02-02
申请人： SanDisk Technologies, Inc.
发明人： Kenneth Louie , Khanh Nguyen , Man Mui
IPC分类号： G11C16/04 , G11C16/10 , G11C16/08 , G11C16/16 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/1157 , H01L27/11582
摘要： When applying a programming voltage at one end of a word line of a non-volatile memory circuit, if the word line has a large RC constant the far end of the word line will not rise as fast as the driven end, which can adversely affect device performance. To more quickly raise the voltage on the selected word line, a voltage kick is applied to non-selected word lines, such as dummy word lines, by way of a non-selected sub-block of the selected block. The channel of NAND strings in the non-selected sub-block is used to transfer the kick to the far end of the selected word line of the selected sub-block.
摘要翻译：当在非易失性存储器电路的字线的一端应用编程电压时，如果字线具有大的RC常数，则字线的远端将不会像驱动端一样快地上升，这可能不利地影响设备性能。为了更快地提高所选字线上的电压，通过所选块的未选择的子块，对未选择的字线（例如虚拟字线）施加电压脚踢。非选择子块中的NAND串的通道用于将踢脚转移到所选子块的选定字线的远端。

90. 发明申请

US20160005464A1 COUNTER FOR WRITE OPERATIONS AT A DATA STORAGE DEVICE 审中-公开
标题翻译：在数据存储设备上进行写操作的计数器
公开(公告)号：US20160005464A1
公开(公告)日：2016-01-07
申请号：US14704808
申请日：2015-05-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： XINDE HU , MANUEL ANTONIO D'ABREU
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0035 , G11C16/3486 , G11C16/349 , G11C2213/71
摘要： A data storage device includes a resistive random access memory (ReRAM). A method includes storing data in the ReRAM by performing a first number of write operations to a storage region of the ReRAM. The storage region is tracked by a counter. The method further includes incrementing a value of the counter a second number of times responsive to storing the data in storage region. The second number is less than the first number.
摘要翻译：数据存储装置包括电阻随机存取存储器（ReRAM）。一种方法包括通过对ReRAM的存储区域执行第一次写入操作来将数据存储在ReRAM中。存储区域由计数器跟踪。该方法还包括响应于将数据存储在存储区域中而将计数器的值递增第二次数。第二个数字小于第一个数字。

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