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1. 发明授权

US09424178B2 Optimized flash memory without dedicated parity area and with reduced array size 有权
标题翻译：优化的闪存，没有专门的奇偶校验区域和减少的阵列大小
公开(公告)号：US09424178B2
公开(公告)日：2016-08-23
申请号：US13806007
申请日：2011-06-21
申请人： Eran Sharon , Idan Alrod , Simon Litsyn
发明人： Eran Sharon , Idan Alrod , Simon Litsyn
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10 , G11C11/56 , G11C16/10 , G11C7/10 , G11C29/00
CPC分类号： G06F12/0246 , G06F11/1072 , G06F11/1076 , G11C7/1006 , G11C11/5628 , G11C16/10 , G11C29/00 , G11C2211/5641 , H03M13/05
摘要： A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.
摘要翻译：一种用于优化闪存而没有专用奇偶校验区和减小阵列大小的方法和系统。多级单元（MLC）闪存的存储器容量减小，控制器操作简化。简化操作包括控制器能够将每个主机数据页面编程为整数个闪存页面。在闪存设备中维护每个单元（IBPC）的最大可用信息位，同时还使闪存的编程吞吐量最大化。特性包括动态选择闪存单元使用哪些单元状态的能力。

2. 发明授权

US09070453B2 Multiple programming of flash memory without erase 有权
标题翻译：多次编程闪存，无需擦除
公开(公告)号：US09070453B2
公开(公告)日：2015-06-30
申请号：US13086408
申请日：2011-04-14
申请人： Eran Sharon , Idan Alrod , Simon Litsyn , Ishai Ilani
发明人： Eran Sharon , Idan Alrod , Simon Litsyn , Ishai Ilani
IPC分类号： G06F12/02 , G11C16/10 , G11C11/56 , G11C16/34
CPC分类号： G11C16/102 , G06F12/02 , G11C11/5628 , G11C16/349
摘要： To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.
摘要翻译：为了顺次地在多个存储单元中存储数量相等的第一和第二多个输入位，第一变换将第一输入位变换为第一多个变换位。单元的第一部分被编程为根据位序列到单元级别的映射来存储第一变换的位，但是如果第一变换具有可变的输出长度，则只有当足够少的第一变换位适合于第一细胞部分。然后，在不擦除包括第一部分的第二单元部分的情况下，如果根据映射，表示通过第二输入位的第二变换获得的第二多个变换位的第二部分的单元的各个级别是从当前单元级可访问，第二部分被编程为存储第二转换位。

3. 发明授权

US08874825B2 Storage device and method using parameters based on physical memory block location 有权
标题翻译：存储设备和方法使用基于物理内存块位置的参数
公开(公告)号：US08874825B2
公开(公告)日：2014-10-28
申请号：US12495502
申请日：2009-06-30
申请人： Idan Alrod , Eran Sharon
发明人： Idan Alrod , Eran Sharon
IPC分类号： G06F11/08 , G11C16/10 , G06F12/06 , G06F11/10
CPC分类号： G06F12/0207 , G06F11/1068 , G06F12/0246 , G06F2212/2022 , G06F2212/7201 , G11C16/10
摘要： A data storage device and methods of performing memory operations using location-based parameters are disclosed. A method includes identifying a set of parameter values associated with a physical block of a memory array on a memory die. The set of parameter values is identified based on a physical location of the physical block. A physical location may include an edge or a central region of the memory array or the memory die. The memory die may comprise a nonvolatile semiconductor memory (e.g., flash memory). Parameter values may include a size or a number of programming steps, pulse widths, maximum programming or erase voltages, reading or verify reference voltages, and parameters relating to error correction, among others, including time dependent parameters. A memory access operation, such as a reading, programming, or erasing operation, is initiated with respect to the physical block in accordance with the set of parameter values.
摘要翻译：公开了使用基于位置的参数来执行存储器操作的数据存储设备和方法。一种方法包括识别与存储器管芯上的存储器阵列的物理块相关联的一组参数值。基于物理块的物理位置来识别参数值集合。物理位置可以包括存储器阵列或存储器管芯的边缘或中心区域。存储器管芯可以包括非易失性半导体存储器（例如闪速存储器）。参数值可以包括编程步骤的大小或数量，脉冲宽度，最大编程或擦除电压，读取或验证参考电压以及与误差校正有关的参数，其中包括时间相关参数。根据该组参数值，相对于物理块启动诸如读取，编程或擦除操作之类的存储器访问操作。

4. 发明授权

US08666068B2 Method for scrambling shaped data 有权
标题翻译：扰码形状数据的方法
公开(公告)号：US08666068B2
公开(公告)日：2014-03-04
申请号：US13331705
申请日：2011-12-20
申请人： Eran Sharon , Idan Alrod , Ariel Navon
发明人： Eran Sharon , Idan Alrod , Ariel Navon
IPC分类号： G06F21/00
CPC分类号： G11B20/0021 , G11B2220/60 , H04K1/06 , H04L9/34
摘要： A method includes, in a data storage device, receiving data having a particular proportion of zero values and one values and scrambling the data to generate scrambled data that has the particular proportion of zero values and one values.
摘要翻译：一种方法包括在数据存储设备中接收具有特定比例的零值和一个值的数据，并对数据进行加扰以产生具有特定比例的零值和一个值的加扰数据。

5. 发明申请

US20140013033A1 OPTIMIZED FLASH MEMORY WITHOUT DEDICATED PARITY AREA AND WITH REDUCED ARRAY SIZE 有权
标题翻译：优化的闪存，没有专用的区域和减少的阵列大小
公开(公告)号：US20140013033A1
公开(公告)日：2014-01-09
申请号：US13806007
申请日：2011-06-21
申请人： Eran Sharon , Idan Alrod , Simon Litsyn
发明人： Eran Sharon , Idan Alrod , Simon Litsyn
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F11/1072 , G06F11/1076 , G11C7/1006 , G11C11/5628 , G11C16/10 , G11C29/00 , G11C2211/5641 , H03M13/05
摘要： A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.
摘要翻译：一种用于优化闪存而没有专用奇偶校验区和减小阵列大小的方法和系统。多级单元（MLC）闪存的存储器容量减小，控制器操作简化。简化操作包括控制器能够将每个主机数据页面编程为整数个闪存页面。在闪存设备中维护每个单元（IBPC）的最大可用信息位，同时还使闪存的编程吞吐量最大化。特性包括动态选择闪存单元使用哪些单元状态的能力。

6. 发明申请

US20140006898A1 FLASH MEMORY WITH RANDOM PARTITION 有权
标题翻译：具有随机分区的闪存
公开(公告)号：US20140006898A1
公开(公告)日：2014-01-02
申请号：US13539969
申请日：2012-07-02
申请人： Eran Sharon , Idan Alrod
发明人： Eran Sharon , Idan Alrod
IPC分类号： H03M13/29 , G06F12/02
CPC分类号： G06F11/1072 , G06F12/0246 , G06F12/0873 , G06F2212/1016 , G06F2212/222 , G06F2212/7202 , H03M13/1102 , H03M13/152 , H03M13/27 , H03M13/2957 , H03M13/35 , H03M13/356
摘要： A system and method for partitioning data in long term memory of a flash memory device is disclosed. The method may include the steps of identifying a type of data that has been received and routing the data to one of at least two partitions in the long term memory array. One partition of the flash memory device may be optimized for random data while another is optimized for sequential data. The method includes identifying the type of data and routing the data to the appropriate partition. Data may be analyzed and routed upon receipt or initially stored in a default partition and later analyzed and routed to another partition. The partition for random data may be configured for storing data using a first level of ECC protection while the second may be configured for storing data using a second, stronger level of ECC protection.
摘要翻译：公开了一种用于在闪存设备的长期存储器中分区数据的系统和方法。该方法可以包括以下步骤：识别已经接收的数据类型，并将数据路由到长期存储器阵列中的至少两个分区中的一个。闪存器件的一个分区可以针对随机数据进行优化，而另一个对顺序数据进行优化。该方法包括识别数据类型并将数据路由到适当的分区。数据可以在接收时被分析和路由，或者最初存储在默认分区中，并且随后被分析并被路由到另一个分区。用于随机数据的分区可以被配置为使用第一级ECC保护来存储数据，而第二层可以被配置为使用第二更强级别的ECC保护来存储数据。

7. 发明申请

US20130294157A1 READING DATA FROM MULTI-LEVEL CELL MEMORY 有权
标题翻译：从多级单元读取数据
公开(公告)号：US20130294157A1
公开(公告)日：2013-11-07
申请号：US13465308
申请日：2012-05-07
申请人： Eran SHARON , Idan ALROD
发明人： Eran SHARON , Idan ALROD
IPC分类号： G11C16/26
CPC分类号： G06F11/1072 , G11C11/5642 , G11C11/5671
摘要： A method at a data storage device includes determining a first hard bit of a first logical page, the first hard bit corresponding to a particular cell of the MLC memory. A second hard bit of a second logical page is sensed. The second hard bit corresponds to the particular cell. The first hard bit is used as a soft bit of the second logical page to provide reliability information during a decode operation of the second logical page.
摘要翻译：数据存储设备的方法包括确定第一逻辑页的第一硬比特，对应于MLC存储器的特定单元的第一硬比特。感测到第二个逻辑页面的第二个硬位。第二个硬比特对应于特定的小区。第一硬比特用作第二逻辑页的软比特，以在第二逻辑页的解码操作期间提供可靠性信息。

8. 发明授权

US08516352B2 Compact decoding of punctured block codes 有权
标题翻译：打孔块码的紧凑解码
公开(公告)号：US08516352B2
公开(公告)日：2013-08-20
申请号：US12506327
申请日：2009-07-21
申请人： Eran Sharon , Idan Alrod , Simon Litsyn
发明人： Eran Sharon , Idan Alrod , Simon Litsyn
IPC分类号： H03M13/03
CPC分类号： H03M13/6362 , G06F11/1068 , H03M13/1111 , H03M13/15
摘要： k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′
摘要翻译： k个输入位根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所得码字被打孔，n'

9. 发明授权

US08508989B2 Post-facto correction for cross coupling in a flash memory 有权
标题翻译：闪存中交叉耦合的事后校正
公开(公告)号：US08508989B2
公开(公告)日：2013-08-13
申请号：US13183341
申请日：2011-07-14
申请人： Idan Alrod , Eran Sharon
发明人： Idan Alrod , Eran Sharon
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/3418 , G11C2211/5634
摘要： A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that data are read from the cells by measuring those values. One of the cells and its neighbors are read. The data stored in the cell are estimated, based on the measurements and on respective extents to which the neighbors disturb the reading. Preferably, the method also includes determining those respective extents to which the neighbors disturb the reading, for example based on the measurements themselves.
摘要翻译：一种使用包括多个单元（例如闪存单元）的存储器来存储和读取数据的方法，使得通过将单元的物理参数（例如阈值电压）的相应值设置为指示来存储在单元中的数据的数据，并且通过测量这些值从单元读取数据。读取其中一个单元及其邻居。存储在单元中的数据基于测量以及相邻的干扰读数的相应范围来估计。优选地，该方法还包括例如基于测量本身来确定邻近者对其进行干扰的相应范围。

10. 发明申请

US20130166988A1 MULTI-PHASE ECC ENCODING USING ALGEBRAIC CODES 有权
标题翻译：使用代数编码的多相ECC编码
公开(公告)号：US20130166988A1
公开(公告)日：2013-06-27
申请号：US13335534
申请日：2011-12-22
申请人： ERAN SHARON , IDAN ALROD , SIMON LITSYN
发明人： ERAN SHARON , IDAN ALROD , SIMON LITSYN
IPC分类号： H03M13/00 , G06F11/10
CPC分类号： G06F11/1012
摘要： A method includes a first encoding operation associated with a first algebraic error correcting code generating a first set of first parity bits corresponding to a first set of information bits and a second set of first parity bits corresponding to a second set of information bits. A second encoding operation associated with a second algebraic error correcting code generates a first set of second parity bits corresponding to the first set of information bits and a second set of second parity bits corresponding to the second set of information bits. A third encoding operation generates a set of joint parity bits. The first set of information bits, the second set of information bits, the first set of first parity bits, the second set of first parity bits, and the joint parity bits may be stored in a data storage device as a single codeword.
摘要翻译：一种方法包括与第一代数纠错码相关联的第一编码操作，所述第一代数纠错码产生对应于第一组信息比特的第一奇偶校验位的第一组，以及与第二组信息比特对应的第二奇偶校验位组。与第二代数纠错码相关联的第二编码操作产生对应于第一组信息比特的第一组第二奇偶校验位和对应于第二组信息比特的第二奇偶校验位组。第三编码操作产生一组联合奇偶校验位。第一组信息位，第二组信息位，第一组第一奇偶校验位，第二组第一奇偶校验位和联合奇偶校验位可以作为单个码字存储在数据存储设备中。

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