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81. 发明授权

US5311483A Synchronous type semiconductor memory 失效
标题翻译：同步型半导体存储器
公开(公告)号：US5311483A
公开(公告)日：1994-05-10
申请号：US890592
申请日：1993-04-12
申请人： Atsushi Takasugi
发明人： Atsushi Takasugi
IPC分类号： G11C7/22 , G11C11/4076 , G11C11/402 , G11C29/00
CPC分类号： G11C11/4076 , G11C7/22
摘要： A DRAM is capable of regulating an output timing of a read data. The output timing of the read data can be regulated by the DRAM which has a circuit (127) for counting the number of clock pulses until the read data is transferred to a data latch circuit (121) and a circuit (129) for outputting the counted number. The DRAM has a circuit (125) which can regulate the output timing in response to an external input signal.
摘要翻译： PCT No.PCT / JP91 / 01584 Sec。 371日期：1993年4月12日 102（e）日期1993年4月12日PCT 1991年11月19日PCT PCT。公开号WO92 / 09083 日期：1992年5月29日。DRAM能够调节读取数据的输出定时。读取数据的输出定时可以由具有用于计数时钟脉冲数的电路（127）的DRAM来调节，直到读取的数据被传送到数据锁存电路（121）和用于输出计数 DRAM具有可以响应于外部输入信号来调节输出定时的电路（125）。

82. 发明授权

US5262988A Dynamic memory cell and dynamic memory 失效
标题翻译：动态内存单元和动态内存
公开(公告)号：US5262988A
公开(公告)日：1993-11-16
申请号：US882867
申请日：1992-05-14
申请人： Kiyofumi Ochii
发明人： Kiyofumi Ochii
IPC分类号： G11C11/402 , G11C11/405 , G11C11/406 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/406 , G11C11/405 , H01L27/108
摘要： A dynamic memory cell includes a first MOS transistor for data transfer connected at one end to a read/write node and having a gate connected to a transfer gate control line, a second MOS transistor having a gate connected to a first storage node on the other end side of the first MOS transistor and a gate capacitor used as a data storage capacitor, a third MOS transistor for refresh current supply connected at one end to the first storage node, and a resistor element or switching element connected between the gate of the third MOS transistor and the other end of the second MOS transistor. The cell itself has the refresh current supplying capability and it is not necessary to effect the refresh operation on the read/write node side by turning on the charge transfer transistor.
摘要翻译：动态存储单元包括用于数据传输的第一MOS晶体管，其一端连接到读/写节点并且具有连接到传输门控制线的栅极;第二MOS晶体管，其栅极连接到第一存储节点第一MOS晶体管的端侧和用作数据存储电容器的栅极电容器，一端连接到第一存储节点的用于刷新电流源的第三MOS晶体管，以及连接在第三MOS晶体管的栅极之间的电阻元件或开关元件 MOS晶体管和第二MOS晶体管的另一端。单元本身具有刷新电流供应能力，并且不需要通过接通电荷转移晶体管来实现读/写节点侧的刷新操作。

83. 发明授权

US4669062A Two-tiered dynamic random access memory (DRAM) cell 失效
标题翻译：两层动态随机存取存储器（DRAM）单元
公开(公告)号：US4669062A
公开(公告)日：1987-05-26
申请号：US778542
申请日：1985-09-20
申请人： Motoo Nakano
发明人： Motoo Nakano
IPC分类号： H01L27/088 , G11C11/402 , G11C11/405 , H01L21/20 , H01L21/8234 , H01L21/8242 , H01L27/00 , H01L27/06 , H01L27/10 , H01L27/108 , G11C11/34
CPC分类号： H01L27/0688 , G11C11/405 , H01L27/108
摘要： A dynamic random access memory (DRAM) cell has three MIS transistors arranged in a two-tiered structure with high packing density. A read select MIS transistor has source, drain and channel regions formed in the substrate and is covered by a first insulating layer and a semiconductor layer. A write select MIS transistor has source and drain regions formed in the semiconducting layer, the first insulating layer having a contact window therein through which the drain regions of the write select and read select MIS transistors are connected. A storage MIS transistor has source, channel and drain regions formed in the substrate, the channel region of the storage MIS transistor comprising the source region of the read select MIS transistor and the drain region of the storage MIS transistor comprising the channel region of the read select MIS transistor, the respective channel regions of the read and storage MIS transistors being formed in a common level in the silicon substrate and directly connected therein between the source region of the storage MIS transistor and the drain region of the read select MIS transistor. The write select MIS transistor further may comprise a separate gate electrode, the gate electrodes of the write and read MIS transistors comprising portions of corresponding, separate conducting lines serving as write select and read select lines, respectively.
摘要翻译：动态随机存取存储器（DRAM）单元具有以具有高堆积密度的双层结构排列的三个MIS晶体管。读选择MIS晶体管具有形成在衬底中的源极，漏极和沟道区，并被第一绝缘层和半导体层覆盖。写入选择MIS晶体管具有形成在半导体层中的源极和漏极区域，第一绝缘层具有接触窗口，通过该接触窗口连接写入选择和读取选择MIS晶体管的漏极区域。存储MIS晶体管具有形成在衬底中的源极，沟道和漏极区，存储MIS晶体管的沟道区包括读选择MIS晶体管的源极区和存储MIS晶体管的漏极区，包括读取的沟道区选择MIS晶体管，读取和存储MIS晶体管的各个沟道区域形成在硅衬底中的公共电平并且直接连接在存储MIS晶体管的源极区域和读选择MIS晶体管的漏极区域之间。写选择MIS晶体管还可以包括单独的栅电极，写和读MIS晶体管晶体管的栅电极分别包括用作写选择和读选择线的相应的单独导电线的部分。

84. 发明授权

US4308594A MOS Memory cell 失效
标题翻译： MOS存储单元
公开(公告)号：US4308594A
公开(公告)日：1981-12-29
申请号：US117223
申请日：1980-01-31
申请人： Ching-Lin Jiang
发明人： Ching-Lin Jiang
IPC分类号： G11C11/41 , G11C11/34 , G11C11/402 , G11C11/412 , H01L27/108 , H01L29/78 , H03K3/356 , G11C11/40 , G11C11/24
CPC分类号： G11C11/412 , G11C11/4023 , H01L27/108 , H03K3/35606 , H03K3/356086
摘要： An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (30) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (30) and the second transistor (22) defines a second node (K). The capacitor (30) provides a coupling path between the first clock line (34) and the second node (K) for conditionally supplying a voltage from the first clock line (34) to the second node (K) to render voltage at the second node (K) higher than the cell voltage supply source (26). A third transistor is provided for the memory cell (10) and is interconnected to the first node (S) and the second node (K) and the second clock line (36). The third transistor (24) provides a charging path between the second clock line (36) and the second node (K) for conditionally maintaining a voltage at the second node (K).
摘要翻译：提供具有位线（12），字线（14）和单元电压供应（26）的集成电路存储单元（10）。集成电路存储单元（10）包括第一时钟线（34）和第二时钟线（36）。第一晶体管（20）互连到位线（12）和字线（14），用于提供对存储单元（10）的访问。第二晶体管（22）与电池电压源（26）和第一晶体管（20）互连，由此限定第一节点（S）。第二晶体管（22）提供从单电池电压源（26）到第一节点（S）的充电路径。提供电容器（30）并将第一时钟线（34）和第二晶体管（22）互连。电容器（30）和第二晶体管（22）之间的互连限定第二节点（K）。电容器（30）在第一时钟线（34）和第二节点（K）之间提供耦合路径，用于从第一时钟线（34）向第二节点（K）有条件地提供电压以在第二时钟线（K）高于电池电压源（26）。第三晶体管被提供给存储单元（10）并且互连到第一节点（S）和第二节点（K）和第二时钟线（36）。第三晶体管（24）在第二时钟线（36）和第二节点（K）之间提供充电路径，用于有条件地维持第二节点（K）的电压。

85. 发明授权

US4030081A Dynamic transistor-storage element 失效
标题翻译：动态晶体管存储元件
公开(公告)号：US4030081A
公开(公告)日：1977-06-14
申请号：US609622
申请日：1975-09-02
申请人： Karlheinrich Horninger
发明人： Karlheinrich Horninger
IPC分类号： G11C11/40 , G11C11/402 , G11C11/403 , G11C11/404 , G11C11/405 , G11C14/00 , G11C16/04 , G11C19/18 , H03K3/356 , G11C11/24 , H03K3/353 , H03K5/00
CPC分类号： G11C11/4023 , G11C11/40 , G11C11/403 , G11C11/404 , G11C11/405 , G11C14/00 , G11C16/0466 , G11C19/184 , H03K3/356008
摘要： A dynamic storage element is characterized in that, in addition to the transistors of the storage element, at least one MI.sub.1 I.sub.2 S storage transistor is provided to receive the data stored in the storage element. The dynamic storage element comprises a transistor and a series-connected capacitor. The transistor is connected on the one hand to the capacitor and on the other hand to a bit line, and the gate terminal of the transistor is connected to a word line. In particular, a MI.sub.1 I.sub.2 S storage transistor is additionally provided which is connected on the one hand to the word line and on the other hand to a point at which the transistor and the capacitor are connected in series and the gate terminal of the MI.sub.1 I.sub.2 S storage transistor is connected to a gate line.
摘要翻译：动态存储元件的特征在于，除了存储元件的晶体管之外，提供至少一个MI1I2S存储晶体管以接收存储在存储元件中的数据。动态存储元件包括晶体管和串联电容器。晶体管一方面连接到电容器，另一方面连接到位线，并且晶体管的栅极端子连接到字线。特别地，另外提供了MI1I2S存储晶体管，其一方面连接到字线，另一方面连接到晶体管和电容器串联连接的点，并且MI1I2S存储晶体管的栅极端子是连接到门线。

86. 发明授权

US4023149A Static storage technique for four transistor IGFET memory cell 失效
标题翻译：四晶体管IGFET存储单元的静态存储技术
公开(公告)号：US4023149A
公开(公告)日：1977-05-10
申请号：US626596
申请日：1975-10-28
申请人： Alan R. Bormann , William L. Martino , Jerry D. Moench
发明人： Alan R. Bormann , William L. Martino , Jerry D. Moench
IPC分类号： G11C11/402 , G11C11/40
CPC分类号： G11C11/4023
摘要： A four-IGFET memory cell is utilized as a static (or DC) memory cell rather than as a dynamic memory cell. When the memory cell is in the standby mode an intermediate voltage is applied to a selection conductor coupled to the gates of the gating IGFETS of the memory cell. The intermediate voltage applied to the "X" selection conductor under standby conditions is slightly in excess of two IGFET threshold voltages, and is sufficient to maintain the stored logical state, yet causes very little power to be dissipated by the memory cell. A full logical "1" level is applied to the selection conductor during either a read operation or a write operation if the memory cell is selected, i.e. is addressed by the decoding circuitry in response to chip select and address inputs of a memory chip incorporating the memory cell. If the memory cell is unselected during a read or write operation, a logical "0" is applied to the selection conductor. A reference voltage circuit is provided on the semiconductor memory chip including an array of the four-IGFET memory cells in a preferred embodiment of the invention. The reference voltage circuit operates so that each row selection conductor, which is coupled to the gating IGFETS of a row of memory cells, is coupled to the reference voltage conductor when the semiconductor chip is unselected by a separate coupling IGFET coupled, respectively, between the reference voltage conductor and each of the selection conductors. Each selection conductor is also coupled to a selection circuit, which couples the selection conductor toward a V.sub.DD power supply voltage if the corresponding row has been selected by the decode circuitry and the chip is "selected". However, if the particular row is not selected, then the corresponding selection conductor is coupled by two IGFETS to a ground voltage supply conductor (if the chip is "selected").
摘要翻译：四IGFET存储单元被用作静态（或DC）存储单元而不是动态存储单元。当存储器单元处于待机模式时，中间电压被施加到耦合到存储器单元的选通IGFETS的栅极的选择导体。在待机状态下施加到“X”选择导体的中间电压稍微超过两个IGFET阈值电压，并且足以维持存储的逻辑状态，但是由存储器单元消耗很少的功率。如果选择了存储单元，则在读取操作或写入操作期间将完全逻辑“1”电平施加到选择导体，即，由解码电路响应于包含该存储器单元的存储器芯片的片选和地址输入来寻址记忆单元如果在读取或写入操作期间存储单元未被选择，逻辑“0”被施加到选择导体。在本发明的优选实施例中，在包括四个IGFET存储单元的阵列的半导体存储器芯片上提供参考电压电路。参考电压电路工作，使得当半导体芯片被分离耦合的分离耦合IGFET选择时，耦合到一行存储单元的选通IGFETS的每个行选择导体耦合到参考电压导体参考电压导体和每个选择导体。每个选择导体还耦合到选择电路，其将选择导体连接到VDD电源电压，如果对应的行已经被解码电路选择并且芯片被“选择”。然而，如果没有选择特定的行，则相应的选择导体由两个IGFETS耦合到接地电压供应导体（如果芯片被“选择”）。

87. 发明授权

US3988604A Electronic calculator or digital processor chip having multiple function arithmetic unit output 失效
标题翻译：具有多功能运算单元输出的电子计算器或数字处理器芯片
公开(公告)号：US3988604A
公开(公告)日：1976-10-26
申请号：US525250
申请日：1974-11-19
申请人： Joseph H. Raymond, Jr.
发明人： Joseph H. Raymond, Jr.
IPC分类号： G11C11/402 , G06F7/38
CPC分类号： G11C11/402
摘要： An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a basic machine a cycle one digit of the RAM is accessed. In the machine cycle the ROM is also addressed to provide an instruction word, and the word is decoded and executed. The output of the arithmetic unit may be coupled to either a one digit accumulator or a one digit RAM address register.
摘要翻译：用于提供电子计算器或数字处理器的功能的MOS / LSI半导体芯片包括用于数据存储的RAM，用于程序指令存储的ROM，用于对数据执行操作的算术单元和用于定义机器功能的控制电路响应来自ROM的指令以及机器中的条件和来自外部的输入。操作是数字化的，因为在基本机器中，访问RAM的一位数字的周期。在机器周期中，ROM也被寻址以提供指令字，并且该字被解码和执行。算术单元的输出可以耦合到一位累加器或一位数字RAM地址寄存器。

88. 发明授权

US3955181A Self-refreshing random access memory cell 失效
标题翻译：自刷新随机存取存储单元
公开(公告)号：US3955181A
公开(公告)日：1976-05-04
申请号：US525245
申请日：1974-11-19
申请人： Joseph H. Raymond, Jr.
发明人： Joseph H. Raymond, Jr.
IPC分类号： G11C11/402 , G11C11/24 , G11C7/00
CPC分类号： G11C11/402
摘要： A memory cell comprising field effect transistors for use in a random access memory array. The cell is of the dynamic type wherein data is stored on capacitive elements, and is self-refreshing; no circuitry external to the array is needed for refresh, other than clock sources. Five MOS field effect transistors are employed, with two non-overlapping clocks, a data buss for each row of the array and one address line for each column. The transistors and associated capacitors are arranged to reinforce a stored "1" or "0".
摘要翻译：一种存储单元，包括用于随机存取存储器阵列的场效应晶体管。该单元是动态类型，其中数据存储在电容元件上，并且是自刷新的; 除了时钟源之外，刷新不需要阵列外部的电路。采用五个MOS场效应晶体管，具有两个非重叠时钟，阵列的每一行的数据总线和每列的一个地址线。晶体管和相关联的电容器被布置成加强存储的“1”或“0”。

89. 发明授权

US3876887A Mos amplifier 失效
标题翻译： MOS放大器
公开(公告)号：US3876887A
公开(公告)日：1975-04-08
申请号：US38034973
申请日：1973-07-18
申请人： INTEL CORP
发明人： REED JOHN A
IPC分类号： G11C11/402 , G11C11/4091 , H03K5/02 , H03K5/20 , H03F3/16
CPC分类号： G11C11/4091 , G11C11/4023 , H03K5/023
摘要： A metal-oxide-semiconductor (MOS) differential amplifier particularly suitable for sensing the state of a memory cell, which includes a pair of column lines, is disclosed. The differential amplifier is biased such that it operates in a linear region and is capacitively coupled to the column lines.

90. 发明授权

US3795898A Random access read/write semiconductor memory 失效
标题翻译：随机访问读/写半导体存储器
公开(公告)号：US3795898A
公开(公告)日：1974-03-05
申请号：US3795898D
申请日：1972-11-03
申请人： ADVANCED MEMORY SYST
发明人： MEHTA R , GEILHUFE M , PALFI T
IPC分类号： G11C11/402 , G11C11/407 , G11C11/408 , G11C11/412 , H03K19/017 , G11C11/34
CPC分类号： G11C11/412 , G11C11/4023 , G11C11/4087
摘要： A Random Access Read/Write Semiconductor Memory for fabrication in integrated circuit form using field effect devices. The memory is a dynamic memory having a provision for maintaining DC stability in the four transistor memory cells so as to not require periodic refreshing. Various unique buffer and timing circuitry is also provided for minimizing power consumption, for compatibility with TTL circuitry, and for providing very fast read/write access from a single clock signal.
摘要翻译：随机存取读/写半导体存储器，采用场效应器件集成电路制造。存储器是具有用于维持四个晶体管存储单元中的DC稳定性的动态存储器，从而不需要周期性刷新。还提供了各种独特的缓冲器和定时电路，用于最小化功耗，与TTL电路兼容，以及从单个时钟信号提供非常快速的读/写访问。

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