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81. 发明申请

US20070243659A1 PHASE-CHANGEABLE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070243659A1
公开(公告)日：2007-10-18
申请号：US11733131
申请日：2007-04-09
申请人： Hee-Ju SHIN , Jong-Chan SHIN , Soon-Oh PARK , Hyeong-Geun AN , Han-Bong KO
发明人： Hee-Ju SHIN , Jong-Chan SHIN , Soon-Oh PARK , Hyeong-Geun AN , Han-Bong KO
IPC分类号： H01L21/06
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.
摘要翻译：在半导体存储器件及其制造方法中，在具有设置有第一焊盘的逻辑区域的衬底上形成绝缘层，并且随后设置有第二焊盘和下电极的单元区域。绝缘层被蚀刻成具有第一开口的第一绝缘层图案，该第一开口露出第一焊盘。第一插头形成在第一开口中。将形成有第一插塞的第一绝缘层图案蚀刻成具有暴露下电极的第二开口的第二绝缘层图案。包括相变材料的第二插头形成在第二开口中。导线和上电极分别形成在第一插头和第二插头上。

82. 发明授权

US07251354B2 Electronic component inspection apparatus 失效
标题翻译：电子元件检测仪器
公开(公告)号：US07251354B2
公开(公告)日：2007-07-31
申请号：US10506809
申请日：2003-03-07
申请人： Yukio Kanno , Yoshiaki Fukukawa
发明人： Yukio Kanno , Yoshiaki Fukukawa
IPC分类号： B65G43/08 , H01L21/06 , G01M19/00 , G01N21/84
CPC分类号： G01R31/2893 , G01R1/0433 , G01R31/01 , G01R31/2851
摘要： An electronic component inspection apparatus includes an inspection socket which inspects a component, a tray disposition area in which a component waits before it is inspected, tray disposition areas which store a component after it has been inspected, components transfer mechanisms each of which has a vacuum or suction nozzle that can pick up and hold a component to transfer the component, a component position confirmation camera which can capture an image of the component that is being transferred, and a controller which transfers a component to the inspection socket, via a position in which the component position confirmation camera captures an image of the component being held by the suction nozzle while the component is being transferred from the tray disposition area to the inspection socket, and based on that captured image, controls the drive of the components transfer mechanisms so that the component is set in the inspection socket.
摘要翻译：电子部件检查装置包括检查部件的检查插座，检查前部件等待的托盘配置区域，检查部件之后存储部件的托盘配置区域，每个具有真空的部件传送机构或可吸收和保持组件以传送组件的吸嘴，可捕获正在传送的组件的图像的组件位置确认摄像机以及通过位置中的位置将组件传送到检查插座的控制器组件位置确认摄像机捕获由吸嘴保持的部件的图像，同时将部件从托盘配置区域传送到检查插座，并且基于该捕获的图像，控制部件传送机构的驱动组件被设置在检查插座中。

83. 发明授权

US07247511B2 Thin film phase-change memory 有权
标题翻译：薄膜相变存储器
公开(公告)号：US07247511B2
公开(公告)日：2007-07-24
申请号：US11485241
申请日：2006-07-11
申请人： Hsiang-Lan Lung , Yi-Chou Chen
发明人： Hsiang-Lan Lung , Yi-Chou Chen
IPC分类号： H01L21/00 , H01L21/06 , H01L21/20 , H01L29/76 , H01L29/94
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0071 , G11C2013/0078 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/1675 , H01L45/1691
摘要： A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etching process. If desired, the chalcogenide structure may be implemented in series with a semiconductor device such as a diode or a selecting transistor. The diode drives a current through the chalcogenide structure. The selecting transistor drives a current through the chalcogenide structure when enabled by a voltage at a gate terminal of the selecting transistor. The selecting transistor has a gate terminal, a source terminal, and a drain terminal; the gate terminal may be operatively coupled to a word line of a memory array, the source terminal may be operatively coupled to a drive line of the memory array, and the drain terminal may be operatively coupled to a bit line of the memory array.
摘要翻译：存储单元包括硫族化物随机存取存储器（CRAM）单元和CMOS电路。 CMOS电路访问CRAM单元。 CRAM单元具有通过薄膜工艺（例如，硫族化物沉积薄膜工艺）和通过等蚀刻工艺确定的横截面积。如果需要，硫族化物结构可以与诸如二极管或选择晶体管的半导体器件串联地实现。二极管驱动通过硫族化物结构的电流。当通过选择晶体管的栅极端子处的电压使能时，选择晶体管驱动通过硫族化物结构的电流。选择晶体管具有栅极端子，源极端子和漏极端子; 栅极端子可以可操作地耦合到存储器阵列的字线，源极端子可操作地耦合到存储器阵列的驱动线，并且漏极端子可以可操作地耦合到存储器阵列的位线。

84. 发明申请

US20070166874A1 Fabrication Method of Nanoimprint Mold Core 审中-公开
标题翻译：纳米压印模芯的制作方法
公开(公告)号：US20070166874A1
公开(公告)日：2007-07-19
申请号：US11626961
申请日：2007-01-25
申请人： Ching-Bin Lin , Pao-Yu Cheng , Hung-Yi Lin
发明人： Ching-Bin Lin , Pao-Yu Cheng , Hung-Yi Lin
IPC分类号： H01L21/06
CPC分类号： G02B6/124 , B82Y10/00 , B82Y20/00 , B82Y30/00
摘要： A method for fabricating a nanoimprint mold core is disclosed. The method includes providing a substrate; forming on the substrate an amorphous thin film, which is transformed into a crystalline thin film upon receipt of energy, the crystalline thin film having physical and chemical characteristics different from those of the amorphous thin film; applying the energy onto a predetermined region of the amorphous thin film, to transform the amorphous thin film within the predetermined region into the crystalline thin film; etching the illuminated amorphous film, which has crystalline mark on amorphous film, and at least partially removing the area of remained amorphous thin films; performing an imprinting process on the substrate, which has the etched amorphous thin films formed; and performing a molding releasing process on the substrate, so as to obtain the nanoimprint mold core.
摘要翻译：公开了一种制造纳米压印模芯的方法。该方法包括提供基板; 在基板上形成无定形薄膜，其在接收到能量时转变成晶体薄膜，该晶体薄膜具有与非晶薄膜不同的物理和化学特性; 将能量施加到非晶薄膜的预定区域上，将预定区域内的非晶薄膜转变成晶体薄膜; 蚀刻在非晶膜上具有结晶标记的照射非晶膜，并且至少部分去除剩余的非晶态薄膜的面积; 在形成有蚀刻的非晶质薄膜的基板上进行压印处理; 在基板上进行成型脱模工序，得到纳米压印模芯。

85. 发明申请

US20070026566A1 Phase change memory with damascene memory element 有权
标题翻译：相变记忆与大马士革记忆元素
公开(公告)号：US20070026566A1
公开(公告)日：2007-02-01
申请号：US11542712
申请日：2006-10-04
申请人： Ilya Karpov , Charles Kuo , Yudong Kim , Fabio Pellizzer
发明人： Ilya Karpov , Charles Kuo , Yudong Kim , Fabio Pellizzer
IPC分类号： H01L21/06
CPC分类号： H01L45/1683 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16
摘要： A phase change material may be formed within a trench in a first layer to form a damascene memory element and in an overlying layer to form a threshold device. Below the first layer may be a wall heater. The wall heater that heats the overlying phase change material may be formed in a U-shape in some embodiments of the present invention. The phase change material for the memory element may be elongated in one direction to provide greater alignment tolerances with said heater and said threshold device.
摘要翻译：相变材料可以形成在第一层中的沟槽内，以形成镶嵌存储元件，并在上层中形成阈值器件。第一层以下可以是壁式加热器。在本发明的一些实施例中，加热上覆相变材料的壁加热器可以形成为U形。用于存储元件的相变材料可以在一个方向上伸长，以与所述加热器和所述阈值装置提供更大的对准公差。

86. 发明授权

US07163837B2 Method of forming a resistance variable memory element 有权
标题翻译：形成电阻变量存储元件的方法
公开(公告)号：US07163837B2
公开(公告)日：2007-01-16
申请号：US10230189
申请日：2002-08-29
申请人： John T. Moore , Kristy A. Campbell , Terry L. Gilton
发明人： John T. Moore , Kristy A. Campbell , Terry L. Gilton
IPC分类号： H01L21/06
CPC分类号： G11C13/0011 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/143 , H01L45/16 , H01L45/1616 , H01L45/1625
摘要： A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a silver layer over a chalcogenide glass layer. Processing the silver layer via heat treating, light irradiation, or a combination of both to form a layer comprising silver interstitially formed in a chalcogenide glass layer; silver-selenide formed in a layer comprising silver interstitially formed in a chalcogenide glass layer; or a silver doped chalcogenide glass layer having silver-selenide formed therein.
摘要翻译：本文公开了一种用于控制电阻变量存储元件中硫族化物玻璃的银掺杂的方法。该方法包括在硫族化物玻璃层上形成银层。通过热处理，光照射或两者的组合来处理银层以形成在硫族化物玻璃层中间隙形成的银的层; 在由硫族化物玻璃层中间隙形成的银层中形成的硒化银; 或其中形成有硒化银的银掺杂硫族化物玻璃层。

87. 发明申请

US20060205110A1 Method for manufacturing an electrolyte material layer in semiconductor memory devices 失效
标题翻译：在半导体存储器件中制造电解质材料层的方法
公开(公告)号：US20060205110A1
公开(公告)日：2006-09-14
申请号：US11076027
申请日：2005-03-10
申请人： Cay-Uwe Pinnow , Klaus-Dieter Ufert
发明人： Cay-Uwe Pinnow , Klaus-Dieter Ufert
IPC分类号： H01L21/06 , H01L21/20 , H01L21/8238 , H01L21/00
CPC分类号： H01L45/085 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/1616 , H01L45/1625 , H01L45/1641
摘要： A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.
摘要翻译：一种用于制造电解质材料层的方法，所述电解质材料层具有结合或沉积在其中用于半导体存储器件，特别是电阻切换存储器件或部件的硫族化物材料。该方法包括以下步骤：制造半导体衬底，在半导体衬底上沉积二元硫族化物层，在二元硫族化物层上沉积含硫层，以及产生包含至少两种不同硫属化物化合物的三元硫族化物层， x 。硫属化物化合物的一个组分A包括IV元素主要组分的材料，例如Ge，Si或过渡金属，优选基团由Zn，Cd，Hg或其组合组成。

88. 发明申请

US20060030068A1 Fabrication method for phase change diode memory cells 失效
公开(公告)号：US20060030068A1
公开(公告)日：2006-02-09
申请号：US11253233
申请日：2005-10-17
申请人： Gary Ashton , Gary Gibson , Robert Bicknell-Tassius
发明人： Gary Ashton , Gary Gibson , Robert Bicknell-Tassius
IPC分类号： H01L21/06
CPC分类号： B82Y10/00 , G11B9/10 , G11B9/14 , G11B9/1463 , G11B9/149 , G11B11/002 , G11B11/08
摘要： A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes is disclosed. The method includes depositing a first diode layer of CuInSe material on a substrate and depositing a second diode layer of phase-change material on the first diode layer.

89. 发明申请

US20050287698A1 Use of chalcogen plasma to form chalcogenide switching materials for nanoscale electronic devices 审中-公开
标题翻译：使用硫族元素等离子体形成用于纳米级电子器件的硫属元素切换材料
公开(公告)号：US20050287698A1
公开(公告)日：2005-12-29
申请号：US10878921
申请日：2004-06-28
申请人： Zhiyong Li , Shih-Yuan Wang
发明人： Zhiyong Li , Shih-Yuan Wang
IPC分类号： H01L21/06 , H01L27/24 , H01L45/00
CPC分类号： B82Y10/00 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/1608
摘要： A method of forming a metal chalcogenide. A metal is provided and exposed to a chalcogen plasma to form the metal chalcogenide.
摘要翻译：形成金属硫族化物的方法。提供金属并暴露于硫属元素等离子体以形成金属硫族化物。

90. 发明申请

US20050202589A1 Technique and apparatus for depositing thin layers of semiconductors for solar cell fabrication 失效
标题翻译：用于沉积太阳能电池制造半导体薄层的技术和设备
公开(公告)号：US20050202589A1
公开(公告)日：2005-09-15
申请号：US11081308
申请日：2005-03-15
申请人： Bulent Basol
发明人： Bulent Basol
IPC分类号： H01L21/06
CPC分类号： H01L31/0322 , H01L21/02568 , H01L21/02614 , H01L21/02628 , Y02E10/541
摘要： The present invention advantageously provides for, in different embodiments, low-cost deposition techniques to form high-quality, dense, well-adhering Group IBIIIAVIA compound thin films with macro-scale as well as micro-scale compositional uniformities. In one embodiment, there is provided a method of growing a Group IBIIIAVIA semiconductor layer on a base, and includes the steps of depositing on the base a film of Group IB material and at least one layer of Group IIIA material, intermixing the film of Group IB material and the at least one layer of Group IIIA material to form an intermixed layer, and forming over the intermixed layer a metallic film comprising at least one of a Group IIIA material sub-layer and a Group IB material sub-layer. Other embodiments are also described.
摘要翻译：本发明在不同的实施方案中有利地提供低成本沉积技术以形成具有宏观尺度以及微尺度组成均匀性的高质量，致密，良好粘附的IBIIIAVIA组合薄膜。在一个实施例中，提供了在基底上生长IBIIIAVIA族半导体层的方法，并且包括以下步骤：在基底上沉积IB族材料的膜和至少一层IIIA族材料，将组的膜 IB材料和所述至少一层IIIA族材料以形成混合层，并且在所述混合层上形成包含IIIA族材料子层和IB族材料子层中的至少一种的金属膜。还描述了其它实施例。

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