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81. 发明授权

US08854387B2 Bundle-based CPU/GPU memory controller coordination mechanism 有权
标题翻译：基于捆绑的CPU / GPU内存控制器协调机制
公开(公告)号：US08854387B2
公开(公告)日：2014-10-07
申请号：US12975806
申请日：2010-12-22
申请人： Jaewoong Chung
发明人： Jaewoong Chung
IPC分类号： G09G5/39 , G06F13/00 , G09G5/00
CPC分类号： G09G5/001 , G09G5/39
摘要： A system and method are disclosed for managing memory requests that are coordinated between a system memory controller and a graphics memory controller. Memory requests are pre-scheduled according to the optimization policies of the source memory controller and then sent over the CPU/GPU boundary in a bundle of pre-scheduled requests to the target memory controller. The target memory controller then processes pre-scheduling decisions contained in the pre-schedule requests, and in turn, issues memory requests as a proxy of the source memory controller. As a result, the target memory controller does not need to perform both CPU requests and GPU requests.
摘要翻译：公开了一种用于管理在系统存储器控制器和图形存储器控制器之间协调的存储器请求的系统和方法。存储器请求根据源存储器控制器的优化策略进行预先安排，然后通过CPU / GPU边界将一批预先调度的请求发送到目标存储器控制器。目标存储器控制器然后处理包含在预调度请求中的预调节决定，并且进而发送存储器请求作为源存储器控制器的代理。因此，目标存储器控制器不需要执行CPU请求和GPU请求。

82. 发明申请

US20140292789A1 STEREOSCOPIC IMAGE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：立体图像显示装置及其驱动方法
公开(公告)号：US20140292789A1
公开(公告)日：2014-10-02
申请号：US14104797
申请日：2013-12-12
申请人： LG Display Co., Ltd.
发明人： Myeongdo KIM , Hanseok KIM , Myungsoo PARK , Seonghwan JU
IPC分类号： H04N13/04 , G09G5/39 , G09G5/18
CPC分类号： H04N13/366 , H04N13/315 , H04N13/351
摘要： Provided is a stereoscopic image display device comprising a display panel displaying a multi-view image in a three-dimensional (3D) mode, a switchable barrier forming a barrier in the 3D mode, a user position detecting unit outputting a user position data including a user position information, a switchable barrier controlling unit calculating an average picture level of the multi-view image in the 3D mode and controlling an aperture ratio of the switchable barrier according to the average picture level and the user position information, a switchable barrier driving unit supplying driving voltages to divided electrodes of the switchable barrier and supplying a common voltage to a barrier common electrode, and a display panel driving unit converting the multi-view image into data voltages to supply the data voltages to data lines of the display panel and sequentially supplying gate pulses to gate lines of the display panel.
摘要翻译：本发明提供了一种立体图像显示装置，其特征在于，包括以三维（3D）模式显示多视点图像的显示面板，在3D模式中形成屏障的切换屏障，输入用户位置数据的用户位置检测单元，用户位置信息，可切换屏障控制单元，计算3D模式中的多视点图像的平均图像电平，并根据平均图像电平和用户位置信息来控制可切换屏障的开口率;可切换屏障驱动单元向可切换屏障的分割电极提供驱动电压并向屏障公共电极提供公共电压;以及显示面板驱动单元，将多视点图像转换为数据电压，以将数据电压提供给显示面板的数据线，并依次向显示面板的栅极线提供栅极脉冲。

83. 发明授权

US08836696B2 Random accessible lossless parameter data compression for tile based 3D computer graphics systems 有权
标题翻译：用于基于瓦片的3D计算机图形系统的随机可访问的无损参数数据压缩
公开(公告)号：US08836696B2
公开(公告)日：2014-09-16
申请号：US13199884
申请日：2011-09-12
申请人： Xile Yang
发明人： Xile Yang
IPC分类号： G06T15/00 , G09G5/39 , G06T9/00
CPC分类号： G06T15/00 , G06T9/00
摘要： A method and apparatus are provided for compressing vertex parameter data in a 3D computer graphic system, where the vertex parameter data is a data block relating to a plurality of vertices used for rendering an image. The data relating to each vertex includes multiple byte data relating to at least one parameter. The parameters include X, Y and Z coordinates and further coordinates for texturing and shading. Decompression is also provided for decompressing vertex parameter data thus compressed. These are able to access randomly the compressed data, rather than having to read a stream of data.
摘要翻译：提供了一种用于压缩3D计算机图形系统中的顶点参数数据的方法和装置，其中顶点参数数据是与用于渲染图像的多个顶点有关的数据块。与每个顶点相关的数据包括与至少一个参数有关的多字节数据。参数包括X，Y和Z坐标以及进一步的纹理和阴影坐标。解压缩也用于解压缩如此压缩的顶点参数数据。这些能够随机访问压缩数据，而不必读取数据流。

84. 发明授权

US08810497B2 Signal control device, liquid crystal display having the same and signal control method using the same 有权
标题翻译：信号控制装置，具有相同的液晶显示器和使用其的信号控制方法
公开(公告)号：US08810497B2
公开(公告)日：2014-08-19
申请号：US13657238
申请日：2012-10-22
申请人： Samsung Display Co., Ltd.
发明人： Jae-Hyoung Park , Woo-Chul Kim
IPC分类号： G09G3/36 , G09G5/39
CPC分类号： G09G5/006
摘要： A signal controlling method for a display device for signal processing between an external system and a display panel that displays an image by receiving a signal from the external system. The method includes receiving N clock signals and N data signals synchronized with the N clock signals from the external system through N channels, N being a natural number no less than 2; writing the received N data signals in N storage units in order of reception time of the N data signals; extracting one clock signal from the N clock signals; and outputting the N data signals written in the N storage units simultaneously in synchronization with the extracted clock signal.
摘要翻译：一种用于显示装置的信号控制方法，用于通过从外部系统接收信号来显示图像的外部系统和显示面板之间的信号处理。该方法包括通过N个通道从N外部系统接收与N个时钟信号同步的N个时钟信号和N个数据信号，N是不小于2的自然数; 以N个数据信号的接收时间的顺序将接收的N个数据信号写入N个存储单元; 从N个时钟信号中提取一个时钟信号; 并且与所提取的时钟信号同步地输出写入N个存储单元中的N个数据信号。

85. 发明申请

US20140225907A1 PROCESSING ORDER WITH INTEGER INPUTS AND FLOATING POINT INPUTS 有权
标题翻译：具有整数输入和浮点输入的处理订单
公开(公告)号：US20140225907A1
公开(公告)日：2014-08-14
申请号：US14257090
申请日：2014-04-21
申请人： ARM Limited
发明人： Andreas Due ENGH-HALSTVEDT , Jorn NYSTAD
IPC分类号： G06F12/08 , G09G5/39
CPC分类号： G06F12/0802 , G06T1/20 , G09G5/39
摘要： A graphics processing unit 2 includes a texture pipeline 6 which performs filter operations upon texture values. If the texture values are integer texture values, then they may be processed by the texture pipeline in a variable order corresponding to the order in which they are retrieved from a memory 4. If the texture values are floating point texture values, then they are processed in a fixed order in order to ensure result invariants as the filter operation is non-associative for floating point values. The filter operation is not commenced until all of the floating point texture values have been retrieved from the memory 4 and other available for processing.
摘要翻译：图形处理单元2包括对纹理值执行滤波操作的纹理管线6。如果纹理值是整数纹理值，则它们可以由纹理流水线以与从存储器4检索的顺序相对应的可变顺序来处理。如果纹理值是浮点纹理值，则它们被处理以固定顺序，以确保结果不变量，因为过滤器操作对于浮点值是非关联的。过滤器操作不会开始，直到从存储器4检索到所有浮点纹理值，并且可以处理的其他值。

86. 发明授权

US08803926B2 Display drive device, display device, driving control method, and electronic device storing correction data for correcting image data and displaying the corrected image data in one of various display modes 有权
标题翻译：显示驱动装置，显示装置，驱动控制方法以及存储用于校正图像数据的校正数据的电子装置，并且以各种显示模式之一显示校正后的图像数据
公开(公告)号：US08803926B2
公开(公告)日：2014-08-12
申请号：US13249993
申请日：2011-09-30
申请人： Kenji Kobayashi
发明人： Kenji Kobayashi
IPC分类号： G09G5/10 , G09G5/00 , G09G5/39 , G09G3/32
CPC分类号： G09G3/32 , G09G3/325 , G09G5/18 , G09G2320/0261 , G09G2320/028 , G09G2320/068 , G09G2320/10 , G09G2340/0492
摘要： A display drive device includes a correction data memory circuit, a data reading control circuit, and an image data correction circuit. The correction data memory circuit stores a plurality of pieces of correction data according to characteristics of pixels in association with positions where the pixels are arranged in a display panel. The data reading control circuit sets a reading order of the plurality of pieces of correction data to an order corresponding to a display form and reads the correction data in the set reading order. The image data correction circuit associates the image data with each of the plurality of pieces of correction data and generates corrected image data obtained by correcting the image data using the corresponding correction data.
摘要翻译：显示驱动装置包括校正数据存储电路，数据读取控制电路和图像数据校正电路。校正数据存储电路根据与显示面板中的像素排列的位置相关联的像素的特性来存储多条校正数据。数据读取控制电路将多个校正数据的读取顺序设置为与显示形式相对应的顺序，并以设定的读取顺序读取校正数据。图像数据校正电路将图像数据与多个校正数据中的每一个相关联，并且生成通过使用对应的校正数据校正图像数据而获得的校正图像数据。

87. 发明授权

US08803896B2 Providing a coherent user interface across multiple output devices 有权
标题翻译：在多个输出设备之间提供一致的用户界面
公开(公告)号：US08803896B2
公开(公告)日：2014-08-12
申请号：US12214327
申请日：2008-06-17
申请人： Michael A. Swingler
发明人： Michael A. Swingler
IPC分类号： G06F13/00 , G06F3/14 , G09G5/00 , G09G5/39 , G09G5/393 , G09G5/399 , G09G5/14 , G09G5/36
CPC分类号： G09G5/14 , G06F3/1423 , G06F3/1446 , G09G2340/0407 , G09G2360/02
摘要： Exemplary embodiments of methods and apparatuses to provide a coherent user interface across output devices having various characteristics are described. Rendering into a first window back buffer is performed to output a window on a first output device having first characteristics, and rendering into a second window back buffer is performed to display the window on a second output device having second characteristics. Pixel values of the window outputted on the first output device are stored in the first window back buffer, and the pixel values of the window outputted on the second output device are stored in the second window back buffer. The size of the first window back buffer is associated with the first characteristics of the first output device, and the size of the second window back buffer is associated with the second characteristics of the second output device.
摘要翻译：描述了在具有各种特征的输出设备之间提供一致的用户界面的方法和设备的示例性实施例。执行渲染到第一窗后缓冲器中以在具有第一特征的第一输出设备上输出窗口，并且执行渲染到第二窗后缓冲器中以在具有第二特征的第二输出设备上显示窗口。在第一输出设备上输出的窗口的像素值被存储在第一窗口后缓冲器中，并且将在第二输出设备上输出的窗口的像素值存储在第二窗口后缓冲器中。第一窗后缓冲器的大小与第一输出设备的第一特性相关联，并且第二窗后缓冲器的大小与第二输出设备的第二特性相关联。

88. 发明授权

US08799685B2 Circuits and methods for providing adjustable power consumption 有权
标题翻译：提供可调节功耗的电路和方法
公开(公告)号：US08799685B2
公开(公告)日：2014-08-05
申请号：US12868292
申请日：2010-08-25
申请人： Greg Sadowski , Stephen David Presant
发明人： Greg Sadowski , Stephen David Presant
IPC分类号： G06F1/00 , G06T1/60 , G09G5/39
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , Y02D10/14 , Y02D10/171
摘要： Circuit and methods provide for adjustable power consumption using a plurality of memory controllers. In one example, a first memory controller has a first power consumption level. A second memory controller has a second power consumption level that differs from the first power consumption level. Memory controller bypass logic is connected to the first and second memory controllers and selects for a memory client at least one of the first and second memory controllers in response to a change in a power conservation condition.
摘要翻译：电路和方法使用多个存储器控制器提供可调节的功耗。在一个示例中，第一存储器控制器具有第一功率消耗水平。第二存储器控制器具有与第一功耗水平不同的第二功率消耗水平。存储器控制器旁路逻辑被连接到第一和第二存储器控制器，并响应于功率节省条件的变化而为存储器客户端选择第一和第二存储器控制器中的至少一个。

89. 发明授权

US08749566B2 System and method for an optimized on-the-fly table creation algorithm 有权
标题翻译：用于优化的即时表创建算法的系统和方法
公开(公告)号：US08749566B2
公开(公告)日：2014-06-10
申请号：US13301429
申请日：2011-11-21
申请人： Anita Chowdhry , Subir Ghosh
发明人： Anita Chowdhry , Subir Ghosh
IPC分类号： G06F13/22 , G09G5/39 , G09G5/393
CPC分类号： G09G5/393 , G06F3/14 , G06F3/1415 , G06F3/1454 , G09G5/026 , G09G5/14 , G09G5/397 , G09G2320/10 , G09G2340/02 , G09G2340/125 , G09G2350/00 , G09G2360/10 , G09G2360/125 , G09G2370/022
摘要： A video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.
摘要翻译：计算机系统中的视频输出系统从帧缓冲器读取像素信息以产生视频输出信号。此外，还可以显示全动态视频。当显示全动态视频窗口时，从帧缓冲器和全动态视频缓冲器读取浪费宝贵的存储器带宽。因此，所公开的系统提供了一种系统和方法，用于识别视频输出系统必须从帧缓冲器读取的位置以及其必须从全运动视频缓冲器读取的位置，同时最小化其从帧缓冲器和全动态视频缓冲。

90. 发明申请

US20140146065A1 MPI COMMUNICATION OF GPU BUFFERS 审中-公开
公开(公告)号：US20140146065A1
公开(公告)日：2014-05-29
申请号：US13689533
申请日：2012-11-29
申请人： NVIDIA CORPORATION
发明人： Rolf VandaVaart , Timothy James Murray , Peter Michael Buckingham
IPC分类号： G09G5/39
CPC分类号： G09G5/393 , G06F9/544 , G09G5/366 , G09G2360/06
摘要： A technique for enhancing the efficiency and speed of data transmission within and across multiple, separate computer systems includes the use of an MPI library/engine. The MPI library/engine is configured to facilitate the transfer of data directly from one location to another location within the same computer system and/or on separate computer systems via a network connection. Data stored in one GPU buffer may be transferred directly to another GPU buffer without having to move the data into and out of system memory or other intermediate send and receive buffers.

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