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81. 发明申请

US20150348979A1 HIGH DENSITY SINGLE-TRANSISTOR ANTIFUSE MEMORY CELL 有权
标题翻译：高密度单晶体抗体存储器细胞
公开(公告)号：US20150348979A1
公开(公告)日：2015-12-03
申请号：US14292395
申请日：2014-05-30
申请人： Silanna Semiconductor U.S.A.., Inc.
发明人： Paul A. Nygaard
IPC分类号： H01L27/112 , H01L29/43
CPC分类号： H01L27/11206 , G11C17/16 , H01L21/84 , H01L23/5252 , H01L27/1203 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： Various methods and devices that involve single transistor diode connected anti-fuse memory cells are disclosed. An exemplary memory cell comprises a thin gate insulator. The memory cell also comprises a bulk region of a first conductivity type in contact with a first side of the thin gate insulator. The memory cell also comprises a polysilicon gate electrode of the first conductivity type in contact with a second side of the thin gate insulator. The memory cell also comprises a source region of a second conductivity type in contact with the bulk region at a junction. The polysilicon gate electrode and the source region are operatively coupled to a programming voltage source that addresses the memory cell by blowing the thin gate insulator. The junction forms a diode for the memory cell. The bulk region can be in an active layer of a semiconductor on insulator structure.
摘要翻译：公开了涉及单晶体二极管连接的反熔丝存储器单元的各种方法和装置。示例性的存储单元包括薄栅极绝缘体。存储单元还包括与薄栅极绝缘体的第一侧接触的第一导电类型的主体区域。存储单元还包括与薄栅极绝缘体的第二侧接触的第一导电类型的多晶硅栅电极。存储单元还包括在接合处与主体区域接触的第二导电类型的源极区域。多晶硅栅电极和源极区域可操作地耦合到编程电压源，该编程电压源通过吹薄栅极绝缘体来寻址存储单元。接点形成用于存储单元的二极管。体区域可以是绝缘体上半导体结构的有源层。

82. 发明申请

US20150270358A1 FABRICATION OF GRAPHENE ELECTRODES ON DIAMOND SUBSTRATE 有权
标题翻译：石墨基片上的石墨电极的制造
公开(公告)号：US20150270358A1
公开(公告)日：2015-09-24
申请号：US14221169
申请日：2014-03-20
申请人： KING ABDULAZIZ UNIVERSITY
发明人： HUSSAIN A. ALBARAKATY
IPC分类号： H01L29/40 , H01L21/324 , H01L21/265 , H01L29/16 , H01L29/43
CPC分类号： H01L21/324 , H01L21/043 , H01L21/2652 , H01L29/1606 , H01L2021/26573
摘要： One or more graphene layers may be formed on a diamond substrate by reforming sp3 hybrid orbitals of C—C bonds in a portion of the diamond substrate into sp2 hybrid orbitals. Forming sp2 hybrid orbitals may be achieved by ion bombardment to damage the sp3 hybrid orbitals of the C—C bonds in the diamond substrate and subsequent heating of the diamond substrate to allow annealing to take place. If more than ten graphene layers are formed on the diamond substrate, the graphene layers may be reduced to ten or less graphene layers. Removal of the graphene layers may be performed by peeling a desired number of layers using an adhesive material.
摘要翻译：可以通过将金刚石衬底的一部分中的C-C键的sp 3杂化轨道重整成sp2混合轨道，在金刚石衬底上形成一个或多个石墨烯层。形成sp2杂化轨道可以通过离子轰击来实现，以破坏金刚石基底中C-C键的sp3杂化轨道，随后加热金刚石基底以允许发生退火。如果在金刚石衬底上形成十多个石墨烯层，则石墨烯层可以被还原成十个或更少的石墨烯层。可以通过使用粘合剂材料剥离所需数量的层来进行去除石墨烯层。

83. 发明授权

US09123645B2 Methods of making semiconductor devices with low leakage Schottky contacts 有权
标题翻译：制造具有低泄漏肖特基接触的半导体器件的方法
公开(公告)号：US09123645B2
公开(公告)日：2015-09-01
申请号：US14086545
申请日：2013-11-21
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Bruce M. Green , Haldane S. Henry , Chun-Li Liu , Karen E. Moore , Matthias Passlack
IPC分类号： H01L21/28 , H01L21/285 , H01L29/423 , H01L29/47 , H01L29/778 , H01L29/06 , H01L29/20 , H01L29/43
CPC分类号： H01L21/28581 , H01L21/28587 , H01L29/0657 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/475 , H01L29/7787
摘要： Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.
摘要翻译：实施例包括制造具有低泄漏肖特基接触的半导体器件的方法。实施例包括提供部分完成的半导体器件，其包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除掩模。使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

84. 发明授权

US09099274B2 Lateral field emission device 有权
标题翻译：侧面场发射装置
公开(公告)号：US09099274B2
公开(公告)日：2015-08-04
申请号：US13978797
申请日：2012-01-10
申请人： Cheol Jin Lee , Dong Hoon Shin
发明人： Cheol Jin Lee , Dong Hoon Shin
IPC分类号： H01L29/06 , H01L29/43 , H01J1/316 , B82Y20/00
CPC分类号： H01J1/316 , B82Y20/00 , H01J2201/30446 , H01J2201/30469
摘要： Described is a lateral field emission device emitting electrons in parallel with respect to a substrate. Electron emission materials having a predetermined thickness are arranged in a direction with respect to the substrate on a supporting portion. An anode is disposed on a side portion of the substrate, the anode corresponding to the electron emission materials.
摘要翻译：描述了相对于衬底平行地发射电子的横向场发射器件。具有预定厚度的电子发射材料在支撑部分上相对于衬底的方向布置。阳极设置在基板的侧部，阳极对应于电子发射材料。

85. 发明授权

US09087902B2 FinFETs with strained well regions 有权
标题翻译：具有紧张井区的FinFET
公开(公告)号：US09087902B2
公开(公告)日：2015-07-21
申请号：US13779015
申请日：2013-02-27
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Jing Lee , Cheng-Hsien Wu , Chih-Hsin Ko , Clement Hsingjen Wann
IPC分类号： H01L21/70 , H01L29/78 , H01L29/66 , H01L29/10 , H01L29/417 , H01L29/778 , H01L29/165 , H01L29/43 , H01L29/06
CPC分类号： H01L29/7842 , H01L21/02532 , H01L21/31051 , H01L21/31053 , H01L21/3212 , H01L21/823412 , H01L21/823431 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/0847 , H01L29/1054 , H01L29/157 , H01L29/161 , H01L29/165 , H01L29/41791 , H01L29/432 , H01L29/66431 , H01L29/66787 , H01L29/66795 , H01L29/7786 , H01L29/7787 , H01L29/7789 , H01L29/7848 , H01L29/7849 , H01L29/785
摘要： A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
摘要翻译：一种器件包括衬底和衬底的一部分上的绝缘区域。第一半导体区域在绝缘区域之间并且具有第一导带。第二半导体区域在第一半导体区域的上方并且邻接，其中第二半导体区域包括高于绝缘区域的顶表面的上部，以形成半导体鳍片。半导体鳍具有拉伸应变，并且具有比第一导带低的第二导带。第三半导体区域在半导体鳍片的上表面和侧壁的上方邻接，其中第三半导体区域具有比第二导带高的第三导带。

86. 发明授权

US09087845B2 Electrically conductive device and manufacturing method thereof 有权
标题翻译：导电装置及其制造方法
公开(公告)号：US09087845B2
公开(公告)日：2015-07-21
申请号：US14560729
申请日：2014-12-04
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
发明人： Xinpeng Wang , Haiyang Zhang
IPC分类号： H01L29/43 , H01L23/528 , H01L23/532
CPC分类号： H01L23/5283 , H01L21/76838 , H01L23/5226 , H01L23/53276 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube portion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.
摘要翻译：提供导电装置及其制造方法。根据示例性实施例，导电装置包括在基底上的石墨烯层，石墨烯层上的蛋白质管部分和穿过蛋白质管部分到石墨烯层的导体，其中导体与石墨烯层。

87. 发明授权

US08933563B2 Three-dimension circuit structure and semiconductor device 有权
标题翻译：三维电路结构及半导体器件
公开(公告)号：US08933563B2
公开(公告)日：2015-01-13
申请号：US13572711
申请日：2012-08-13
申请人： Wei-Chou Lan , Ted-Hong Shinn , Henry Wang , Chia-Chun Yeh
发明人： Wei-Chou Lan , Ted-Hong Shinn , Henry Wang , Chia-Chun Yeh
IPC分类号： H01L29/43 , H01L23/485 , H01L23/532
CPC分类号： H01L29/78603 , H01L29/42384 , H01L29/4908
摘要： A three-dimension circuit structure includes a substrate, a first conductive layer, a filled material and a second conductive layer. The substrate has an upper surface and a cavity located at the upper surface. The first conductive layer covers the inside walls of the cavity and protrudes out the upper surface. The filled material fills the cavity and covers the first conductive layer. The second conductive layer covers the filled material and a portion of the first conductive layer, and the first conductive layer and the second conductive layer encapsulate the filled material. The material of the filled material is different from that of the first conductive layer and the second conductive layer.
摘要翻译：三维电路结构包括衬底，第一导电层，填充材料和第二导电层。基板具有位于上表面的上表面和空腔。第一导电层覆盖空腔的内壁并从上表面突出。填充材料填充空腔并覆盖第一导电层。第二导电层覆盖填充材料和第一导电层的一部分，并且第一导电层和第二导电层封装填充材料。填充材料的材料与第一导电层和第二导电层的材料不同。

88. 发明申请

US20150002211A1 METHOD AND SYSTEM FOR RECOVERING FROM TRANSISTOR AGING USING HEATING 有权
标题翻译：使用加热从晶体管老化恢复的方法和系统
公开(公告)号：US20150002211A1
公开(公告)日：2015-01-01
申请号：US13929013
申请日：2013-06-27
申请人： Bradley P. Smith , Mehul D. Shroff
发明人： Bradley P. Smith , Mehul D. Shroff
IPC分类号： H01L29/43 , G05F1/10
CPC分类号： H01L21/28176
摘要： A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).
摘要翻译：提供了一种用于延长在栅极电介质中经受捕获的载流子的半导体器件的可用寿命的机制。本发明的实施例从一个或多个源向栅介质区提供热量，其中热源与半导体器件一起包括在封装中。已经确定，当在晶体管的沟道区域处于积聚模式或不通过沟道提供电流的时段期间施加的热量可以至少部分地将器件从俘获的电荷载体效应中恢复。本发明的实施例使用可用于使用半导体器件的机构（例如，在现场）向受影响的栅极电介质区域供热。

89. 发明授权

US08883609B2 Method for manufacturing a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US08883609B2
公开(公告)日：2014-11-11
申请号：US14086144
申请日：2013-11-21
申请人： Infineon Technologies Austria AG
发明人： Mathias Plappert , Hans-Joachim Schulze
IPC分类号： H01L21/76 , H01L21/02 , H01L21/265 , H01L21/28 , H01L21/324 , H01L29/43 , H01L29/04 , H01L21/04
CPC分类号： H01L21/02595 , H01L21/02532 , H01L21/02592 , H01L21/02598 , H01L21/02609 , H01L21/02667 , H01L21/04 , H01L21/187 , H01L21/265 , H01L21/28 , H01L21/324 , H01L29/04 , H01L29/43 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
摘要翻译：根据实施例，一种制造半导体结构的方法包括提供在参考方向上具有第一晶格常数的第一单晶半导体部分，并形成在参考方向上具有第二晶格常数的第二单晶半导体部分，其与第一晶格常数，在第一单晶半导体部分上。

90. 发明授权

US08785944B2 High electron mobility transistor 有权
标题翻译：高电子迁移率晶体管
公开(公告)号：US08785944B2
公开(公告)日：2014-07-22
申请号：US13707162
申请日：2012-12-06
申请人： Samsung Electronics Co., Ltd.
发明人： In-jun Hwang , Jae-joon Oh , Jae-won Lee , Hyo-ji Choi , Jong-bong Ha
IPC分类号： H01L29/778 , H01L29/20 , H01L29/423 , H01L29/43
CPC分类号： H01L27/0629 , H01L29/1066 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/778 , H01L29/7787
摘要： A high electron mobility transistor (HEMT) according to example embodiments includes a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, and a reverse diode gate structure on the second semiconductor layer. A source and a drain may be on at least one of the first semiconductor layer and the second semiconductor layer. A gate electrode may be on the reverse diode gate structure.
摘要翻译：根据示例实施例的高电子迁移率晶体管（HEMT）包括第一半导体层，第一半导体层上的第二半导体层和第二半导体层上的反向二极管栅极结构。源极和漏极可以在第一半导体层和第二半导体层中的至少一个上。栅电极可以在反向二极管栅极结构上。

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