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    • 81. 发明申请
    • DATA TRANSMISSION IN AN SDH NETWORK
    • SDH网络中的数据传输
    • US20110142081A1
    • 2011-06-16
    • US13032096
    • 2011-02-22
    • Ghani A.M. ABBAS
    • Ghani A.M. ABBAS
    • H04J3/02
    • H04J3/1611H04J2203/0089H04J2203/0094
    • A method for the transmission of data in a synchronous digital hierarchy (SDH) network comprising the steps of transmitting to a node of the network a form of data signal from outside the network, converting the signal into a virtually concatenated information structure and transporting the signal through the network in the virtually concatenated information structure; means for carrying out the method and tributary cards arranged and configured to process signals received in contiguously concatenated form to convert them into virtually concatenated form for transfer across the network; thus providing for data transmitted in high-bandwidth, contiguously concatenated signals (ie VC-4-4c) to be transported across a SDH network, not itself capable of carrying contiguously concatenated signals.
    • 一种用于在同步数字分层(SDH)网络中传输数据的方法,包括以下步骤:从网络外部向网络的节点发送数据信号的形式,将信号转换成虚拟级联的信息结构并传送信号 通过网络中的虚拟级联信息结构; 用于执行布置和配置为处理以连续格式连接的形式接收的信号的方法和辅助卡的装置,以将它们转换为虚拟的级联形式,用于跨网络传送; 从而提供在高带宽,连续级联的信号(即VC-4-4c)中传输的数据,以在SDH网络上传输,本身不能承载连续的级联信号。
    • 84. 发明授权
    • Data transmission in an SDH network
    • SDH网络中的数据传输
    • US07920604B2
    • 2011-04-05
    • US11541355
    • 2006-09-29
    • Ghani A. M. Abbas
    • Ghani A. M. Abbas
    • H04J3/02
    • H04J3/1611H04J2203/0089H04J2203/0094
    • A method for the transmission of data in a synchronous digital hierarchy (SDH) network comprising the steps of transmitting to a node of the network a form of data signal from outside the network, converting the signal into a virtually concatenated information structure and transporting the signal through the network in the virtually concatenated information structure; means for carrying out the method and tributary cards arranged and configured to process signals received in contiguously concatenated form to convert them into virtually concatenated form for transfer across the network; thus providing for data transmitted in high-bandwidth, contiguosly concatenated signals (ie VC-4-4c) to be transported across a SDH network, not itself capable of carrying contiguously concatenated signals.
    • 一种用于在同步数字分层(SDH)网络中传输数据的方法,包括以下步骤:从网络外部向网络的节点发送数据信号的形式,将信号转换成虚拟级联的信息结构并传送信号 通过网络中的虚拟级联信息结构; 用于执行布置和配置为处理以连续格式连接的形式接收的信号的方法和辅助卡的装置,以将它们转换为虚拟的级联形式,用于跨网络传送; 从而提供在高带宽,连续级联的信号(即VC-4-4c)中传输的数据,以在SDH网络上传输,本身不能承载连续的级联信号。
    • 86. 发明授权
    • Highly integrated, high-speed, low-power serdes and systems
    • 高度集成,高速,低功耗的serdes和系统
    • US07848367B2
    • 2010-12-07
    • US11896162
    • 2007-08-30
    • Craig A. HornbuckleDavid A. RoweThomas W. Krawczyk, Jr.Samuel A. SteidlInho Kim
    • Craig A. HornbuckleDavid A. RoweThomas W. Krawczyk, Jr.Samuel A. SteidlInho Kim
    • H04J3/02
    • H04J3/0685H04J3/047Y10S370/907
    • High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.
    • 公开了高速,高性能,低功率转发器,串行器和解串器。 串行器可以包括serdes成帧器接口(SFI)电路,时钟乘法器单元和复用电路。 解串器可以包括用于接收和调整输入数据信号的输入接收器电路,用于恢复时钟和数据信号的时钟和数据恢复电路(CDR),用于将一个或多个数据信道分成更多数量的数据信道的解复用电路 以及用于产生参考信道并产生要发送到成帧器的输出数据信道的Serdes成帧器接口(SFI)电路。 输入接收机电路可以包括限幅放大器。 串行器和解串器中的每一个还可以包括伪随机模式发生器和错误检查器单元。 串行器和解串器各自可以集成到其相应的半导体芯片中,或者两者可以集成到单个半导体芯片中。