专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09935890B2 Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method 有权
公开(公告)号：US09935890B2
公开(公告)日：2018-04-03
申请号：US15092696
申请日：2016-04-07
申请人： Panasonic Corporation
发明人： Peter Klenner
IPC分类号： H04L12/863 , H03M13/27 , H04L1/00
CPC分类号： H04L47/6245 , H03M13/27 , H03M13/271 , H03M13/2732 , H03M13/276 , H03M13/2785 , H03M13/2796 , H04L1/0071 , H04L1/0076 , H04L1/0085 , H04L47/6255
摘要： A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a first connection destination of an input terminal of the convolutional interleaver to one end of one of a plurality of branches; a plurality of FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a second connection destination of an output terminal of the convolutional interleaver to the other end of one of the plurality of branches. The first and second switches switch the first and second connection destinations, respectively, when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the first and second connection destinations sequentially and repeatedly among the plurality of branches.

2. 发明申请

US20180049065A1 OPERATION METHODS OF TERMINAL AND BASE STATION IN MOBILE COMMUNICATION NETWORKS 审中-公开
公开(公告)号：US20180049065A1
公开(公告)日：2018-02-15
申请号：US15673013
申请日：2017-08-09
申请人： Electronics and Telecommunications Research Institute
发明人： Chan Ho YOON , Young Jo KO
IPC分类号： H04W28/16 , H03M13/27 , H03M13/00 , H04L5/00
CPC分类号： H04W28/16 , H03M13/2732 , H03M13/276 , H03M13/6525 , H04J11/005 , H04J13/16 , H04L5/0001 , H04L5/0007 , H04L5/0055 , H04W72/04
摘要： Disclosed are operation methods of a terminal and a base station in mobile communications. The operation method of the terminal in a mobile communication network, comprises receiving a terminal identifier from a base station; generating a plurality of interleaving parameters based on the terminal identifier; dividing a channel-coded data block into a plurality of sub-blocks, and performing a block interleaving on each of the plurality of sub-blocks using the plurality of interleaving parameters; and transmitting the plurality of sub-blocks on which the block interleaving has been performed, wherein an interleaving pattern of the block interleaving for each of the plurality of sub-blocks is determined by the plurality of interleaving parameters.

3. 发明申请

US20170012737A1 TIME AND CELL DE-INTERLEAVING CIRCUIT AND METHOD FOR PERFORMING TIME AND CELL DE-INTERLEAVING 审中-公开
标题翻译：时间和细胞去交互电路和执行时间和细胞去交互的方法
公开(公告)号：US20170012737A1
公开(公告)日：2017-01-12
申请号：US15202954
申请日：2016-07-06
申请人： MStar Semiconductor, Inc.
发明人： Chun-Chieh Wang
IPC分类号： H04L1/00 , H03M13/27
CPC分类号： H03M13/6552 , H03M13/1165 , H03M13/152 , H03M13/2757 , H03M13/276 , H03M13/2778 , H03M13/2906 , H03M13/6561 , H04L1/0045 , H04L1/0052 , H04L1/0057 , H04L1/0071
摘要： A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.
摘要翻译：提供了一种对包括多个单元的交错信号执行时间和单元去交织的方法。该方法包括：提供用于存储单元的第一存储器，每次以一个单元组为单位写入和读取的第一存储器，所述单元组包括K个单元，其中K是大于1的正整数; 提供用于存储从第一存储器读取的单元的第二存储器; 从第一存储器读取单元，并根据多个置换规则的写入规则将单元写入第二存储器，写入到来自相同单元组的第二存储器的K个连续单元; 以及根据所述置换规则的读取规则从所述第二存储器读取所述单元，以使得从所述第二存储器读取的单元完成时间去交织和单元去交织。

4. 发明授权

US09054927B2 Data processing apparatus and method for use in an interleaver suitable for multiple operating modes 有权
标题翻译：用于适用于多种操作模式的交织器的数据处理装置和方法
公开(公告)号：US09054927B2
公开(公告)日：2015-06-09
申请号：US14531236
申请日：2014-11-03
申请人： Sony Corporation
发明人： Samuel Asanbeng Atungsiri , Matthew Paul Athol Taylor , John Nicholas Wilson
IPC分类号： H04L27/00 , H04L27/26 , H04L1/00 , H04L5/00
CPC分类号： H04L5/0007 , G11C19/00 , H03M13/276 , H04L1/0071 , H04L5/0053 , H04L27/14 , H04L27/2602 , H04L27/2647
摘要： A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.
摘要翻译：数据处理装置将要传送的输入符号映射到正交频分复用（OFDM）符号的预定数量的副载波信号。数据处理器包括交织器存储器，其读入预定数量的数据符号以映射到OFDM子载波信号上。交织器存储器将数据符号读出到OFDM子载波上以实现映射，读出的顺序与读入不同，顺序是从一组地址确定的，其效果是数据符号被交织在子载波信号上。地址集合由包括线性反馈移位寄存器和置换电路的地址发生器产生。

5. 发明授权

US08874858B2 Reconfigurable interleaver having reconfigurable counters 有权
标题翻译：具有可重配置计数器的可重构交错器
公开(公告)号：US08874858B2
公开(公告)日：2014-10-28
申请号：US13157085
申请日：2011-06-09
申请人： Nur Engin
发明人： Nur Engin
IPC分类号： H03M13/27 , G06F12/00 , H03M13/00
CPC分类号： H03M13/2789 , H03M13/271 , H03M13/2725 , H03M13/2739 , H03M13/276 , H03M13/2764 , H03M13/2771 , H03M13/2775 , H03M13/6519 , H03M13/6525
摘要： A reconfigurable interleaver is provided, configured to produce a sequence of interleaved addresses, configurable for at least two different interleaving patterns. The reconfigurable interleaver comprises a plurality of reconfigurable counters. The number of values that the counters count is configurable as are their start values. The interleaver further comprises a plurality of memory in which the counters indicate memory positions so that values may be retrieved. Computational elements compute an interleaved sequence of addresses in dependency on the retrieved values. By reconfiguring the counters and possibly changing the content of the memories, the interleaver may be configured for a different interleaving pattern.
摘要翻译：提供可重构交错器，其被配置为产生可配置用于至少两个不同交织模式的交错地址序列。可重配置交织器包括多个可重配置计数器。计数器计数的值的数量可以是其起始值。交织器还包括多个存储器，其中计数器指示存储器位置，从而可以检索值。计算元素根据检索到的值计算交织的地址序列。通过重新配置计数器并且可能改变存储器的内容，交织器可以被配置为不同的交织模式。

6. 发明授权

US08601344B1 Method and apparatus for a parameterized interleaver design process 有权
公开(公告)号：US08601344B1
公开(公告)日：2013-12-03
申请号：US13955862
申请日：2013-07-31
申请人： Hughes Network Systems, LLC
发明人： Rohit Iyer Seshardri , Mustafa Eroz , Lin-Nan Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/2767 , H03M13/275 , H03M13/276 , H03M13/2789
摘要： A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations.

7. 发明申请

US20130318416A1 Rate Matching And Channel Interleaving For A Communications System 审中-公开
标题翻译：通信系统的速率匹配和信道交换
公开(公告)号：US20130318416A1
公开(公告)日：2013-11-28
申请号：US13683011
申请日：2012-11-21
申请人： Wen Tong , Catherine Leretaille , Stephane Gosne
发明人： Wen Tong , Catherine Leretaille , Stephane Gosne
IPC分类号： H03M13/27
CPC分类号： H03M13/2739 , H03M13/00 , H03M13/271 , H03M13/275 , H03M13/276 , H03M13/2764 , H03M13/2792 , H03M13/2957 , H03M13/635 , H04L1/0041 , H04L1/0052 , H04L1/0068 , H04L1/0071
摘要： A method, an apparatus, and a computer program product for matching a rate of data bits to a desired rate by deletion of redundant data bits or repetition of data bits are disclosed. In a non-interleaved matrix of the data bits, a pattern of bits to be deleted or repeated to provide the desired data rate is determined. An address of each bit in the pattern in a manner inverse to the interleaving process is decoded to produce a respective address of the bit in the matrix. The respective bit in the interleaved data bits is deleted or repeated depending upon the respective address. The address decoding is performed in the same manner as a coding of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits.
摘要翻译：公开了一种通过删除冗余数据位或重复数据位来将数据比特速率与期望速率相匹配的方法，装置和计算机程序产品。在数据比特的非交织矩阵中，确定要删除或重复以提供所需数据速率的比特模式。以与交织处理相反的方式的图案中的每个位的地址被解码以产生矩阵中的位的相应地址。取决于相应的地址，删除或重复交错数据位中的相应位。以与用于从数据比特的非交织矩阵产生交错数据比特的地址的编码相同的方式执行地址解码。

8. 发明授权

US08473829B2 Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves 失效
标题翻译：具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成
公开(公告)号：US08473829B2
公开(公告)日：2013-06-25
申请号：US12941178
申请日：2010-11-08
申请人： Tak K. Lee , Ba-Zhong Shen
发明人： Tak K. Lee , Ba-Zhong Shen
IPC分类号： H03M13/00
CPC分类号： H03M13/2771 , H03M13/276 , H03M13/2957 , H03M13/6561 , H04L1/005 , H04L1/0066
摘要： Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. Anticipatory address generation is employed using an index function , that is based on an address mapping , which corresponds to an interleave inverse order of decoding processing (π−1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function , that is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function also allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.
摘要翻译：具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成。使用基于地址映射的索引函数来采用预期地址生成，该地址映射对应于解码处理（pi-1）的交织逆序。根据并行turbo解码处理，代替通过依次从存储体单元访问数据元素来执行自然次序相位解码处理，基于索引函数执行地址的访问，该索引函数是基于映射和交织（pi ）。换句话说，来自存储体位置的访问数据元素对于自然顺序相位解码处理不是顺序的。索引函数还允许通过从存储体单元顺序访问数据元素来执行交织（pi）阶相位解码处理。

9. 发明授权

US08443253B2 Turbo decoding device and communication device 有权
标题翻译： Turbo解码设备和通信设备
公开(公告)号：US08443253B2
公开(公告)日：2013-05-14
申请号：US12876541
申请日：2010-09-07
申请人： Kazuaki Imafuku , Kazuhisa Obuchi , Shunji Miyazaki , Hideaki Yamada , Mutsumi Saito , Masaru Inoue , Shingo Hotta
发明人： Kazuaki Imafuku , Kazuhisa Obuchi , Shunji Miyazaki , Hideaki Yamada , Mutsumi Saito , Masaru Inoue , Shingo Hotta
IPC分类号： H03M13/27 , H03M13/29
CPC分类号： H03M13/2957 , H03M13/276 , H03M13/2775 , H03M13/6525 , H03M13/6566
摘要： A turbo decoding device includes a memory unit that stores data in an interleaving process performed in a process of decoding a coded signal encoded with a turbo code and an access unit that accesses the memory unit to read and write the data. The memory unit includes memory circuits and is formed as one memory space by coupling the memory circuits. Furthermore, the memory circuit functions as a first bank configuration by which a first capacity is assigned to each bank or a second bank configuration by which a second capacity is assigned to each bank in accordance with a combination of the memory circuits. Moreover, the access unit selects by which of the first bank configuration and the second bank configuration the memory unit functions in accordance with a communication method of a coded signal and accesses the memory unit in accordance with the selected bank configuration.
摘要翻译： turbo解码装置包括存储单元，该存储单元将数据存储在对以turbo码编码的编码信号进行解码的处理中执行的交织处理以及访问存储器单元以读取和写入数据的存取单元。存储器单元包括存储器电路，并通过耦合存储器电路而形成为一个存储器空间。此外，存储电路用作第一存储体配置，通过该第一存储体配置，根据存储器电路的组合，将第一容量分配给每个存储体或第二存储体配置，通过该配置将第二容量分配给每个存储体。此外，访问单元根据编码信号的通信方法选择第一存储体配置和第二存储体配置中的哪一个，存储单元根据所选择的存储体配置访问存储单元。

10. 发明授权

US08321725B2 Turbo code interleaver with optimal performance 有权
标题翻译：具有最佳性能的Turbo码交织器
公开(公告)号：US08321725B2
公开(公告)日：2012-11-27
申请号：US11980917
申请日：2007-10-31
申请人： Mustafa Eroz , A. Roger Hammons, Jr. , Feng-Wen Sun
发明人： Mustafa Eroz , A. Roger Hammons, Jr. , Feng-Wen Sun
IPC分类号： H03M13/27
CPC分类号： H03M13/271 , H03M13/2735 , H03M13/2746 , H03M13/276 , H03M13/2767 , H03M13/2771 , H03M13/2789 , H03M13/2957
摘要： A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.
摘要翻译：公开了一种交织具有不同长度的索引数据块的方法。该方法包括以下步骤：提供一组基本交错器，其包括索引数据的一个或多个排列的族，并具有可变长度; 基于所需的交织器长度L选择基本交织器之一; 并且使所选择的基本交织器适配以产生具有期望的交织器长度L的交织器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式