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1. 发明授权

US08336017B2 Architecture optimizer 失效
标题翻译：架构优化器
公开(公告)号：US08336017B2
公开(公告)日：2012-12-18
申请号：US13008900
申请日：2011-01-19
申请人： Suresh Kadiyala , Pius Ng , Anand Pandurangam , Satish Padmanabhan , James Player
发明人： Suresh Kadiyala , Pius Ng , Anand Pandurangam , Satish Padmanabhan , James Player
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法以自动生成由计算机可读代码或模型描述的定制集成电路（IC）。 IC具有一个或多个时序和硬件限制。该系统从静态简档和计算机可读代码的动态简档中提取定义处理器架构的参数; 通过以层次的方式改变架构的一个或多个参数来迭代地优化处理器架构，直到使用架构优化器（AO）满足表示为成本函数的所有定时和硬件约束; 并将生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

2. 发明授权

US08185862B2 Architectural level power-aware optimization and risk mitigation 失效
标题翻译：建筑级电力感知优化和风险减轻
公开(公告)号：US08185862B2
公开(公告)日：2012-05-22
申请号：US12835640
申请日：2010-07-13
申请人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
发明人： Ananth Durbha , Pius Ng , Gary Oblock , Suresh Kadiyala , Satish Padmanabhan
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了通过接收包括计算机可读代码的定制集成电路的规范并生成计算机可读代码的简档以确定指令使用来自动合成定制集成电路的系统和方法; 自动生成针对所述计算机可读代码独特定制的处理器架构，所述处理器架构具有一个或多个处理块以实现一个或多个指令; 基于代码简档确定指令执行序列，并重新分配指令序列以将操作扩展到IC上的不同块以减少热点; 并将生成的处理器芯片规范合成到用于半导体制造的定制集成电路的计算机可读描述中。

3. 发明申请

US20140074900A1 ARCHITECTURE GUIDED OPTIMAL SYSTEM PRECISION DEFINITION ALGORITHM FOR CUSTOM INTEGRATED CIRCUIT 审中-公开
标题翻译：架构引导定制集成电路的最优系统精度定义算法
公开(公告)号：US20140074900A1
公开(公告)日：2014-03-13
申请号：US13782927
申请日：2013-03-01
申请人： ALGOTOCHIP CORPORATION
发明人： Anand Pandurangan , Satish Padmanabhan , Siva Selvaraj , Pius Ng
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F17/5045 , G06F2217/86
摘要： Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法，以通过确定模型或代码中的动态范围与静态范围的比率来自动确定要在定制集成电路（IC）中实现的模型或代码的最佳数字格式表示，以及选择浮点或基于该比率的固定点数表示; 基于包括与预定位精度算术相关联的硬件面积和功率成本的成本函数来确定最佳数量表示格式; 自动生成定制为最佳数字表示格式的处理器架构; 以及将所生成的处理器架构合成到用于半导体制造的定制集成电路的计算机可读描述中。

4. 发明授权

US08370784B2 Automatic optimal integrated circuit generator from algorithms and specification 失效
标题翻译：自动优化集成电路发生器的算法和规范
公开(公告)号：US08370784B2
公开(公告)日：2013-02-05
申请号：US12835621
申请日：2010-07-13
申请人： Satish Padmanabhan , Plus Ng , Anand Pandurangan , Suresh Kadiyala , Ananth Durbha , Tak Shigihara
发明人： Satish Padmanabhan , Plus Ng , Anand Pandurangan , Suresh Kadiyala , Ananth Durbha , Tak Shigihara
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5045
摘要： Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了系统和方法，以基于算法过程或代码作为输入自动设计定制集成电路，并且使用几乎不需要人为参与的高度自动化的工具。该方法包括接收包括计算机可读代码和定制集成电路上的一个或多个约束的定制集成电路的规范; 自动生成最适合约束的计算机可读代码的计算机体系结构; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 连续评估和优化一个或多个因素，包括物理实现，以及在RTL或门级合成之上的架构级别的本地和全局区域，时序或功率; 自动生成软件开发工具包（SDK）和相关固件，以执行定制集成电路上的计算机可读代码; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

5. 发明申请

US20130346926A1 Automatic optimal integrated circuit generator from algorithms and specification 审中-公开
标题翻译：自动优化集成电路发生器的算法和规范
公开(公告)号：US20130346926A1
公开(公告)日：2013-12-26
申请号：US13672822
申请日：2012-11-09
申请人： ALGOTOCHIP CORPORATION
发明人： Anand Pandurangan , Satish Padmanabhan , Siva Selvaraj , Shailesh I. Shah , Krishna Kumar Gadiyaram , Gagan Bihari Rath , Fuk Ho Pius Ng , Ananth Durbha , Suresh Kadiyala
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F8/30 , G06F17/5022
摘要： Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed.
摘要翻译：公开了系统和方法，以基于算法过程或代码作为输入自动设计定制集成电路，并且使用几乎不需要人为参与的高度自动化的工具。

6. 发明申请

US20130263067A1 AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION 审中-公开
标题翻译：自动优化集成电路发生器从算法和规范
公开(公告)号：US20130263067A1
公开(公告)日：2013-10-03
申请号：US13626878
申请日：2012-09-25
申请人： Satish Padmanabhan , Pius Ng , Anand Pandurangan , Suresh Kadiyala , Ananth Durbha , Tak Shigihara
发明人： Satish Padmanabhan , Pius Ng , Anand Pandurangan , Suresh Kadiyala , Ananth Durbha , Tak Shigihara
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/5045
摘要： Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.
摘要翻译：公开了通过接收定制集成电路的规范来自动设计定制集成电路的系统和方法，包括计算机可读代码和定制集成电路上的一个或多个约束; 自动生成具有可编程处理器的计算机体系结构和用于最适合约束的计算机可读代码的一个或多个协处理器; 基于代码简档自动确定指令执行序列，并重新分配或延迟指令序列以在一个或多个处理块上扩展操作以减少热点; 为定制集成电路上的计算机可读代码自动生成相关的测试套件和向量; 并自动合成设计的架构并生成用于半导体制造的定制集成电路的计算机可读描述。

7. 发明授权

US08276107B2 Integrated data model based framework for driving design convergence from architecture optimization to physical design closure 失效
标题翻译：基于集成数据模型的框架，用于从架构优化到物理设计关闭驱动设计融合
公开(公告)号：US08276107B2
公开(公告)日：2012-09-25
申请号：US12906785
申请日：2010-10-18
申请人： Ananth Durbha , Satish Padmanabhan , Pius Ng
发明人： Ananth Durbha , Satish Padmanabhan , Pius Ng
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455 , G06F7/62
CPC分类号： G06F17/5045 , G06F2217/06 , G06F2217/86
摘要： Systems and methods are disclosed to automatically synthesize a custom integrated circuit by encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to computer readable code. The system receives a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed. The look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model.
摘要翻译：公开了系统和方法，以通过在数据模型中编码架构级知识来自动合成定制集成电路，以生成和传递用于物理合成针对计算机可读代码独特定制的芯片规范的新约束。在进行详细的物理合成之后，系统在架构优化期间接收与之前流程中观察到的成本一致的预先成本函数。先行成本函数是从先前的迭代生成的，并通过数据模型提供给后续的迭代。

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