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1. 发明授权

US09666570B2 Memory device and method of manufacturing the same 有权
公开(公告)号：US09666570B2
公开(公告)日：2017-05-30
申请号：US14918567
申请日：2015-10-21
申请人： Winbond Electronics Corp.
发明人： Bo-Lun Wu , Chia-Hua Ho , Ting-Ying Shen , Meng-Hung Lin
IPC分类号： H01L25/18 , H01L27/02 , H01L27/105 , H01L45/00 , H01L27/24
CPC分类号： H01L25/18 , H01L27/0248 , H01L27/101 , H01L27/1052 , H01L27/2418 , H01L27/2463 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1675
摘要： The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.

2. 发明授权

US09575535B2 Integrated circuit and operation method thereof 有权
标题翻译：集成电路及其操作方法
公开(公告)号：US09575535B2
公开(公告)日：2017-02-21
申请号：US14320663
申请日：2014-07-01
申请人： Nuvoton Technology Corporation
发明人： Cheng-Chih Wang
IPC分类号： G06F1/26 , G06F1/30 , H03K17/24 , G06F1/32
CPC分类号： G06F1/305 , G06F1/3203 , H03K17/24
摘要： An integrated circuit and an operation method thereof are provided. The integrated circuit includes a voltage detecting unit, a central processing unit, a memory unit and a control unit. The voltage detecting unit detects a system voltage and correspondingly outputs a voltage state signal. The central processing unit has at least one register. When the system voltage is downed to a voltage level lower than or equal to a brown-out voltage and greater than a reset low voltage, the control unit stores values of the registers into the memory unit.
摘要翻译：提供了一种集成电路及其操作方法。集成电路包括电压检测单元，中央处理单元，存储单元和控制单元。电压检测单元检测系统电压并相应地输出电压状态信号。中央处理单元至少有一个寄存器。当系统电压降低到低于或等于欠压电压并大于复位低电压的电压电平时，控制单元将寄存器的值存储到存储器单元中。

3. 发明授权

US09231679B1 Multiple input multiple output wireless communication system and channel decomposition method thereof 有权
标题翻译：多输入多输出无线通信系统及其信道分解方法
公开(公告)号：US09231679B1
公开(公告)日：2016-01-05
申请号：US14698855
申请日：2015-04-29
申请人： Winbond Electronics Corp.
发明人： Chia-Hsiang Yang , Yu-Cheng Tsai
IPC分类号： H04B7/02 , H04B7/04 , H04L25/02
CPC分类号： H04L25/0204 , H04B7/0413
摘要： A multiple input multiple output wireless communication system and a channel decomposition method thereof are provided. The wireless communication system includes a precoding unit, a channel estimation unit, a channel decomposition unit and a quantization unit. The precoding unit receives a plurality of transmission data streams and wireless channel information to provide a plurality of transmission symbols to a wireless channel. The channel estimation unit estimates the wireless channel to provide a channel matrix. The channel decomposition unit makes a plurality of elements on a diagonal and adjacent to a side of the diagonal as real numbered elements through an element ration and correspondingly rotates a first unit matrix and a second unit matrix to obtain channel state information. The quantization unit provides the wireless channel information according to the channel state information.
摘要翻译：提供了多输入多输出无线通信系统及其信道分解方法。无线通信系统包括预编码单元，信道估计单元，信道分解单元和量化单元。预编码单元接收多个传输数据流和无线信道信息，以向无线信道提供多个传输符号。信道估计单元估计无线信道以提供信道矩阵。信道分解单元通过元素比例使对角线上的多个元素与对角线的一侧相邻，作为实数元素，并相应地旋转第一单位矩阵和第二单位矩阵以获得信道状态信息。量化单元根据信道状态信息提供无线信道信息。

4. 发明授权

US09076572B2 Conductive paste 有权
标题翻译：导电胶
公开(公告)号：US09076572B2
公开(公告)日：2015-07-07
申请号：US14221276
申请日：2014-03-20
申请人： Chi Mei Corporation
发明人： Chan-Li Hsueh , Chung-Ping Li , Chu-Yun Cheng
IPC分类号： H01B1/22 , H05K3/12
CPC分类号： H01B1/22 , H05K3/1283
摘要： A conductive paste is provided, which includes 3 wt % to 20 wt % of epoxy resin, 10 wt % to 25 wt % of solvent, 0.3 wt % to 5 wt % of latent curing agent, 3.5 wt % to 35 wt % of flaky metal powder surface-treated by saturated fatty acid, and 35 wt % to 75 wt % of flaky metal powder surface-treated by unsaturated fatty acid.
摘要翻译：提供导电性糊料，其包含3重量％至20重量％的环氧树脂，10重量％至25重量％的溶剂，0.3重量％至5重量％的潜伏性固化剂，3.5重量％至35重量％的片状用饱和脂肪酸表面处理的金属粉末和不饱和脂肪酸表面处理的片状金属粉末的35重量％〜75重量％。

5. 发明授权

US09069422B2 Projected capacitive touch device and touch control methods for projected capacitive panel thereof 有权
标题翻译：投影电容式触摸装置及其投影电容面板的触摸控制方法
公开(公告)号：US09069422B2
公开(公告)日：2015-06-30
申请号：US13413628
申请日：2012-03-06
申请人： Chih-Chia Chang , Chen-Pang Kung , Chang-An Ho , Heng-Yin Chen
发明人： Chih-Chia Chang , Chen-Pang Kung , Chang-An Ho , Heng-Yin Chen
IPC分类号： G06F3/045 , G06F3/044 , G06F3/041
CPC分类号： G06F3/044 , G06F3/0416
摘要： A projected capacitive touch device, a projected capacitive touch panel and touch control methods thereof are disclosed. The touching control method includes mixing a detecting signal and a feedback driving signal to generate a sending signal; transmitting the sending signal to at least one touch sensing unit of the projected capacitive touch panel, wherein an electrical field is generated on the touch sensing unit according to the feedback driving signal so that a feedback tactile sense according to the electrical field can be obtained by a user while touching the touch sensing unit.
摘要翻译：公开了投影电容式触摸装置，投影电容式触摸面板及其触摸控制方法。触摸控制方法包括混合检测信号和反馈驱动信号以产生发送信号; 将发送信号发送到投影电容式触摸面板的至少一个触摸感测单元，其中根据反馈驱动信号在触摸感测单元上产生电场，使得根据电场的反馈触觉可以通过用户在触摸触摸感测单元时。

6. 发明授权

US09001298B1 Pixel structure, display panel and manufacturing method of pixel structure 有权
标题翻译：像素结构，显示面板和像素结构的制造方法
公开(公告)号：US09001298B1
公开(公告)日：2015-04-07
申请号：US14077191
申请日：2013-11-11
申请人： Au Optronics Corporation
发明人： Yan-Yu Peng , Hsing-Lung Lee
IPC分类号： G02F1/1343 , G02F1/1333
CPC分类号： G02F1/134363 , G02F2001/134372
摘要： A pixel structure includes a scan line, a first insulation layer, a data line, a pixel electrode, a second insulation layer, and a common electrode. The scan line and the first insulation layer are disposed on a first substrate and the first insulation layer covers the scan line. The data line and the pixel electrode are disposed on the first insulation layer. The second insulation layer covers the data line and the pixel electrode and has a first opening located between the data line and the pixel electrode. The common electrode is disposed on the second insulation layer and has slits exposing a portion of the pixel electrode. The common electrode covers the data line and has a first extending portion filled in the first opening such that the first extending portion of the common electrode is located between the data line and the pixel electrode.
摘要翻译：像素结构包括扫描线，第一绝缘层，数据线，像素电极，第二绝缘层和公共电极。扫描线和第一绝缘层设置在第一基板上，第一绝缘层覆盖扫描线。数据线和像素电极设置在第一绝缘层上。第二绝缘层覆盖数据线和像素电极，并且具有位于数据线和像素电极之间的第一开口。公共电极设置在第二绝缘层上并且具有暴露像素电极的一部分的狭缝。公共电极覆盖数据线，并且具有填充在第一开口中的第一延伸部分，使得公共电极的第一延伸部分位于数据线和像素电极之间。

7. 发明授权

US08899992B2 Connector 有权
标题翻译：连接器
公开(公告)号：US08899992B2
公开(公告)日：2014-12-02
申请号：US13794823
申请日：2013-03-12
申请人： Chung-Chih Yang , Chung-Yuan Kuang , Kuo-Chu Liao
发明人： Chung-Chih Yang , Chung-Yuan Kuang , Kuo-Chu Liao
IPC分类号： H01R12/00 , H01R13/15 , H01R24/46
CPC分类号： H01R13/15 , H01R24/46
摘要： A connector adapted to be disposed in a mobile device to electrically connect with a signal terminal of an electronic device is provided. The connector includes a casing, a tube, a pin and a terminal set. The casing has a first side, a second side and a through hole, and the tube is disposed in the second side. The pin has a first end and a second end. The first end is slidably disposed in the through hole and the second end protrudes out of the tube. The terminal set includes a first terminal and a second terminal, and the second terminal is movably connected with the first terminal. When the mobile device is assembled to the electronic device, the signal terminal of the electronic device leans against the pin, so that the pin leans against the first terminal to separate the first terminal and the second terminal.
摘要翻译：提供一种适于设置在与电子设备的信号端子电连接的移动设备中的连接器。连接器包括壳体，管，销和端子组。壳体具有第一侧，第二侧和通孔，并且管设置在第二侧。销具有第一端和第二端。第一端可滑动地设置在通孔中，并且第二端从管中突出。端子组包括第一端子和第二端子，第二端子与第一端子可移动地连接。当移动设备组装到电子设备时，电子设备的信号端子靠在销上，使得引脚靠在第一端子上以分开第一端子和第二端子。

8. 发明授权

US08804059B2 Pixel structure having metal-insulator-semiconductor capacitor 有权
标题翻译：具有金属 - 绝缘体 - 半导体电容器的像素结构
公开(公告)号：US08804059B2
公开(公告)日：2014-08-12
申请号：US13025178
申请日：2011-02-11
申请人： Hsiao-Wei Cheng , Sung-Hui Lin , Ming-Yung Huang , Pin-Miao Liu , Wen-Shin Wu , Chun-Yao Huang , Wei-Sheng Yu
发明人： Hsiao-Wei Cheng , Sung-Hui Lin , Ming-Yung Huang , Pin-Miao Liu , Wen-Shin Wu , Chun-Yao Huang , Wei-Sheng Yu
IPC分类号： G02F1/1343 , H01L29/04 , H01L29/10 , H01L31/00 , H01L27/14 , H01L29/15 , H01L31/036
CPC分类号： G02F1/136213
摘要： A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
摘要翻译：提供了包括扫描线，数据线，有源器件，像素电极，电容器电极线，半导体图案层和至少一个电介质层的像素结构。有源器件电连接到扫描线和数据线。像素电极电连接到有源器件。电容器电极线位于像素电极下方。在电容器电极线和像素电极之间形成第一存储电容器。半导体图案层设置在电容器电极线和像素电极之间，像素电极电连接到半导体图案层。在半导体图案层和电容器电极线之间形成第二存储电容器。电介质层配置在电容电极线与像素电极之间，位于半导电图案层与电容电极线之间。

9. 发明授权

US08791737B2 Phase-locked loop and method for clock delay adjustment 有权
标题翻译：锁相环和时钟延迟调整方法
公开(公告)号：US08791737B2
公开(公告)日：2014-07-29
申请号：US13590185
申请日：2012-08-20
申请人： Wen-Chang Cheng
发明人： Wen-Chang Cheng
IPC分类号： H03L7/06
CPC分类号： H03L7/0995
摘要： A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. In a phase frequency detector, a control signal is generated in accordance with a phase difference and a frequency difference between the output clock signal and a feedback signal generated by a voltage controlled oscillator coupled to the phase frequency detector. The control signal is then fed through a charge pump and a loop filter to generate a voltage control signal according to the control signal. Moreover, in an adjustable delay element, a blended delay signal is generated according to a clock signal and the voltage control signal.
摘要翻译：公开了一种用于时钟延迟调整的锁相环（PLL）及其方法。该方法包括以下步骤。产生参考时钟信号和时钟信号。参考时钟信号通过N分频器馈送以产生具有参考时钟信号的频率1 / N的输出时钟信号。在相位频率检测器中，根据相位差和输出时钟信号与耦合到相位频率检测器的压控振荡器产生的反馈信号之间的频率差产生控制信号。然后通过电荷泵和环路滤波器馈送控制信号，以根据控制信号产生电压控制信号。此外，在可调延迟元件中，根据时钟信号和电压控制信号产生混合延迟信号。

10. 发明授权

US08704966B2 Pixel array, active device array substrate and flat display panel 有权
标题翻译：像素阵列，有源器件阵列基板和平板显示面板
公开(公告)号：US08704966B2
公开(公告)日：2014-04-22
申请号：US13300674
申请日：2011-11-21
申请人： Chuan-Sheng Wei , Ming-Tao Chiang , Yu-Ting Lin , Maw-Song Chen , Wei-Ming Huang
发明人： Chuan-Sheng Wei , Ming-Tao Chiang , Yu-Ting Lin , Maw-Song Chen , Wei-Ming Huang
IPC分类号： G02F1/136
CPC分类号： H01L29/41733 , G02F1/13624 , H01L27/124
摘要： A pixel array including a pixel electrode and an active device is provided. The active device includes a gate, a channel layer, a source, a drain, a connection electrode, a first branch portion and a second branch portion. The gate is electrically connected with a scan line. The channel layer located at a side of the gate is electrically isolated from the gate. The source, the drain and the connection electrode are disposed on a part region of the channel layer. The first branch portion disposed on a part region of the channel layer is connected with an end of the connection electrode. The first branch portion surrounds the source located on the channel layer. The second branch portion disposed on a part region of the channel layer is connected with the other end of the connection electrode. The second branch portion surrounds the drain located on the channel layer.
摘要翻译：提供了包括像素电极和有源器件的像素阵列。有源器件包括栅极，沟道层，源极，漏极，连接电极，第一分支部分和第二分支部分。栅极与扫描线电连接。位于栅极侧的沟道层与栅极电绝缘。源极，漏极和连接电极设置在沟道层的一部分区域上。设置在沟道层的一部分区域上的第一分支部分与连接电极的一端连接。第一分支部分围绕位于通道层上的源。设置在沟道层的一部分区域上的第二分支部分与连接电极的另一端连接。第二分支部分围绕位于通道层上的漏极。

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