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1. 发明授权

US08473695B2 Memory system including variable write command scheduling 有权
标题翻译：内存系统包括可变写入命令调度
公开(公告)号：US08473695B2
公开(公告)日：2013-06-25
申请号：US13077261
申请日：2011-03-31
申请人： Michael J. Morrison , Jay B. Patel
发明人： Michael J. Morrison , Jay B. Patel
IPC分类号： G06F13/00 , G06F13/28 , G06F12/00
CPC分类号： G06F13/16 , G06F13/4239
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.
摘要翻译：系统包括主机设备，其可以被配置为向系统存储器发起存储器请求。该系统还包括可被配置为接收存储器请求并且将存储器请求格式化成通过存储器接口传送到存储器设备的存储器事务的存储器控制器。存储器事务包括多个存储器写入命令类型。每个存储器写入命令类型对应于用于传送对应的数据有效载荷的不同的相应调度。

2. 发明授权

US09553566B2 Hybrid driver circuit 有权
标题翻译：混合驱动电路
公开(公告)号：US09553566B2
公开(公告)日：2017-01-24
申请号：US14564618
申请日：2014-12-09
申请人： MoSys, Inc.
发明人： Eric D. Groen , Charles W. Boecker
IPC分类号： H03K3/012 , H03K19/00 , H03K19/003 , H03K17/687
CPC分类号： H03K3/012 , G05F1/577 , G05F1/59 , H03K17/687 , H03K19/0016 , H03K19/00361 , H03K19/00369
摘要： In one embodiment, a voltage mode driver circuit includes a first voltage adjusting circuit configured to provide an adjustable first pseudo-supply voltage to a first node based on a first supply voltage, including generating the first pseudo-supply voltage based on a first reference voltage and feedback from the first node. In this embodiment, the voltage mode driver circuit includes switching circuitry configured to selectively couple one of the first node or a second node to a first differential output terminal and a different one of the first node or the second node to a second differential output terminal based on a data signal. In this embodiment, the voltage mode driver circuit includes a current mode emphasis driver configured to selectively couple one of the first differential output terminal or the second differential output terminal to a first set of one or more current supplies and a different one of the first differential output terminal or second differential output terminal to a second set of one or more current supplies, based on one or more emphasis signals.
摘要翻译：在一个实施例中，电压模式驱动器电路包括第一电压调整电路，其被配置为基于第一电源电压向第一节点提供可调节的第一伪电源电压，包括基于第一参考电压产生第一伪电源电压和来自第一个节点的反馈。在该实施例中，电压模式驱动器电路包括被配置为选择性地将第一节点或第二节点之一耦合到第一差分输出端和第一节点或第二节点中的不同一个到第二差分输出终端的开关电路在数据信号上。在该实施例中，电压模式驱动器电路包括电流模式强调驱动器，其被配置为选择性地将第一差分输出端或第二差分输出端中的一个耦合到第一组一个或多个电流源和第一差分输出端子或第二差分输出端子连接到基于一个或多个强调信号的一个或多个电流源的第二组。

3. 发明授权

US08635417B2 Memory system including variable write command scheduling 有权
标题翻译：内存系统包括可变写入命令调度
公开(公告)号：US08635417B2
公开(公告)日：2014-01-21
申请号：US13468850
申请日：2012-05-10
申请人： Michael J. Morrison , Jay B. Patel
发明人： Michael J. Morrison , Jay B. Patel
IPC分类号： G06F13/00 , G06F13/28 , G06F12/00
CPC分类号： G06F13/16 , G06F13/4239
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.
摘要翻译：系统包括主机设备，其可以被配置为向系统存储器发起存储器请求。该系统还包括可被配置为接收存储器请求并且将存储器请求格式化成通过存储器接口传送到存储器设备的存储器事务的存储器控制器。存储器事务包括多个存储器写入命令类型。每个存储器写入命令类型对应于用于传送对应的数据有效载荷的不同的相应调度。

4. 发明授权

US09354823B2 Memory system including variable write burst and broadcast command scheduling 有权
标题翻译：内存系统包括可变写突发和广播命令调度
公开(公告)号：US09354823B2
公开(公告)日：2016-05-31
申请号：US13911218
申请日：2013-06-06
申请人： MoSys, Inc.
发明人： Michael J Miller , Michael J Morrison , Jay B Patel
IPC分类号： G06F13/28 , G06F3/06 , G06F13/16 , G06F9/30
CPC分类号： G06F3/0659 , G06F3/0644 , G06F9/3004 , G06F13/1626 , G06F13/1642 , G06F13/28
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a memory write burst command having a first frame that includes a corresponding opcode positioned in one of a first command slot or a second command slot. The memory write burst command may also include a number of subsequent frames for conveying a data payload, as specified for example, by the opcode. The control unit may be configured to generate a number of concurrent sequential memory write operations to the memory in response to receiving the memory write burst command.
摘要翻译：系统包括主机设备，其可以被配置为向系统存储器发起存储器请求。该系统还包括可被配置为接收存储器请求并且将存储器请求格式化成通过存储器接口传送到存储器设备的存储器事务的存储器控制器。存储器事务包括具有第一帧的存储器写突发命令，该第一帧包括位于第一命令槽或第二命令槽之一中的对应操作码。存储器写突发命令还可以包括用于传送例如由操作码指定的数据有效载荷的多个后续帧。控制单元可以被配置为响应于接收到存储器写入突发命令而向存储器生成多个并行顺序存储器写入操作。

5. 发明授权

US08370725B2 Communication interface and protocol 有权
标题翻译：通信接口和协议
公开(公告)号：US08370725B2
公开(公告)日：2013-02-05
申请号：US12697763
申请日：2010-02-01
申请人： Michael J. Miller , Michael J. Morrison , Philip A. Ferolito , Jay B. Patel , Toru M. Kuzuhara
发明人： Michael J. Miller , Michael J. Morrison , Philip A. Ferolito , Jay B. Patel , Toru M. Kuzuhara
IPC分类号： G11C13/00
CPC分类号： H04L1/1607 , H04L2001/0096 , H04L2001/125
摘要： An apparatus includes a receiver, an error detection unit, and an acknowledgement unit. The receiver may receive frames of data from a transmitter unit of a second apparatus via a first communication path. The error detection unit may detect data errors in the frames of data received via the first communication path. The acknowledgment unit may maintain an acknowledgement indicator indicative of whether frames received by the apparatus are error free. In response to the error detection unit detecting an error, the acknowledgement unit may indicate an error condition exists by freezing a value of the acknowledgement indicator, or alternatively the acknowledgement unit may set a current value of the acknowledgement indicator to a predetermined error value. Further, the apparatus may successively convey values of the acknowledgement indicator to the second apparatus via a second communication path while the apparatus is receiving frames.
摘要翻译：一种装置包括接收机，错误检测单元和确认单元。接收机可以经由第一通信路径从第二装置的发射机单元接收数据帧。错误检测单元可以检测通过第一通信路径接收的数据的帧中的数据错误。确认单元可以保持指示由设备接收的帧是否是无错误的确认指示符。响应于错误检测单元检测到错误，确认单元可以通过冻结确认指示符的值来指示存在错误条件，或者可选地，确认单元可以将确认指示符的当前值设置为预定的错误值。此外，当设备正在接收帧时，该设备可以经由第二通信路径将确认指示符的值连续传送到第二设备。

6. 发明授权

US08217814B1 Low power serial to parallel converter 有权
标题翻译：低功率串并转换器
公开(公告)号：US08217814B1
公开(公告)日：2012-07-10
申请号：US12971847
申请日：2010-12-17
申请人： Mahmudul Hassan
发明人： Mahmudul Hassan
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A serial-to-parallel converter includes a sampling unit that may, in response to a serial clock signal, sample a serial data stream and provide an even serial data stream, and an odd serial data stream. The serial-to-parallel converter also includes a strobe generator and a number of latches. The strobe generator generates a plurality of enable signals based upon the serial clock signal. The frequency of a given enable signal corresponds to a fractional multiple of a frequency of the serial clock signal. In response to a particular respective enable signal, each of a first portion of the latches may latch and output a particular respective even data bit. Each of a second portion of the latches may latch and output a particular respective odd data bit. The serial-to-parallel converter further includes a number of output flip-flops to output the data bits in parallel in response to an output clock signal.
摘要翻译：串并转换器包括可以响应于串行时钟信号采样串行数据流并提供偶数串行数据流和奇数串行数据流的采样单元。串并转换器还包括选通发生器和多个锁存器。选通发生器基于串行时钟信号产生多个使能信号。给定使能信号的频率对应于串行时钟信号的频率的分数倍。响应于特定的相应使能信号，锁存器的第一部分中的每一个可以锁存并输出特定的相应偶数数据位。锁存器的第二部分中的每一个可以锁存并输出特定的相应奇数数据位。串并转换器还包括多个输出触发器，以响应于输出时钟信号并行输出数据位。

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