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1. 发明授权

US10050773B1 Bootstrapped autonegotiation clock from a referenceless clock chip 有权
公开(公告)号：US10050773B1
公开(公告)日：2018-08-14
申请号：US15199979
申请日：2016-06-30
申请人： MoSys, Inc.
发明人： Scott A Irwin , Charles W Boecker
IPC分类号： H04L7/00 , H04L7/033 , H04L7/027 , H03L7/08
摘要： A method, system and apparatus, for bootstrapping an autonegotiation signal in an intermediate device. The intermediate device initializes using a referenceless clock circuit. The intermediate device then recovers a more accurate clock sourced from a second device via a clock data recovery circuit in the intermediate device. The second device has a physical medium attachment interface within the intermediate device that does not require autonegotiation. The autonegotiation signal is communicated to a first device having a physical medium dependent interface to the intermediate device, thus requiring autonegotiation.

2. 发明授权

US09553566B2 Hybrid driver circuit 有权
标题翻译：混合驱动电路
公开(公告)号：US09553566B2
公开(公告)日：2017-01-24
申请号：US14564618
申请日：2014-12-09
申请人： MoSys, Inc.
发明人： Eric D. Groen , Charles W. Boecker
IPC分类号： H03K3/012 , H03K19/00 , H03K19/003 , H03K17/687
CPC分类号： H03K3/012 , G05F1/577 , G05F1/59 , H03K17/687 , H03K19/0016 , H03K19/00361 , H03K19/00369
摘要： In one embodiment, a voltage mode driver circuit includes a first voltage adjusting circuit configured to provide an adjustable first pseudo-supply voltage to a first node based on a first supply voltage, including generating the first pseudo-supply voltage based on a first reference voltage and feedback from the first node. In this embodiment, the voltage mode driver circuit includes switching circuitry configured to selectively couple one of the first node or a second node to a first differential output terminal and a different one of the first node or the second node to a second differential output terminal based on a data signal. In this embodiment, the voltage mode driver circuit includes a current mode emphasis driver configured to selectively couple one of the first differential output terminal or the second differential output terminal to a first set of one or more current supplies and a different one of the first differential output terminal or second differential output terminal to a second set of one or more current supplies, based on one or more emphasis signals.
摘要翻译：在一个实施例中，电压模式驱动器电路包括第一电压调整电路，其被配置为基于第一电源电压向第一节点提供可调节的第一伪电源电压，包括基于第一参考电压产生第一伪电源电压和来自第一个节点的反馈。在该实施例中，电压模式驱动器电路包括被配置为选择性地将第一节点或第二节点之一耦合到第一差分输出端和第一节点或第二节点中的不同一个到第二差分输出终端的开关电路在数据信号上。在该实施例中，电压模式驱动器电路包括电流模式强调驱动器，其被配置为选择性地将第一差分输出端或第二差分输出端中的一个耦合到第一组一个或多个电流源和第一差分输出端子或第二差分输出端子连接到基于一个或多个强调信号的一个或多个电流源的第二组。

3. 发明申请

US20160188481A1 Integrated Main Memory And Coprocessor With Low Latency 有权
公开(公告)号：US20160188481A1
公开(公告)日：2016-06-30
申请号：US14872137
申请日：2015-09-30
申请人： MoSys, Inc.
发明人： Michael J Miller , Jay B Patel , Michael J Morrison
IPC分类号： G06F12/08
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/067 , G06F9/3877 , G06F12/00 , G06F12/0875 , G06F12/0895 , G06F2212/1024 , G06F2212/452 , G06F2212/604 , H04L29/12 , H04L67/1017 , H04L67/2842
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

4. 发明申请

US20160164498A1 HYBRID DRIVER CIRCUIT 有权
标题翻译：混合驱动电路
公开(公告)号：US20160164498A1
公开(公告)日：2016-06-09
申请号：US14564618
申请日：2014-12-09
申请人： MoSys, Inc.
发明人： Eric D. Groen , Charles W. Boecker
IPC分类号： H03K3/012 , H03K17/687
CPC分类号： H03K3/012 , G05F1/577 , G05F1/59 , H03K17/687 , H03K19/0016 , H03K19/00361 , H03K19/00369
摘要： In one embodiment, a voltage mode driver circuit includes a first voltage adjusting circuit configured to provide an adjustable first pseudo-supply voltage to a first node based on a first supply voltage, including generating the first pseudo-supply voltage based on a first reference voltage and feedback from the first node. In this embodiment, the voltage mode driver circuit includes switching circuitry configured to selectively couple one of the first node or a second node to a first differential output terminal and a different one of the first node or the second node to a second differential output terminal based on a data signal. In this embodiment, the voltage mode driver circuit includes a current mode emphasis driver configured to selectively couple one of the first differential output terminal or the second differential output terminal to a first set of one or more current supplies and a different one of the first differential output terminal or second differential output terminal to a second set of one or more current supplies, based on one or more emphasis signals.
摘要翻译：在一个实施例中，电压模式驱动器电路包括第一电压调整电路，其被配置为基于第一电源电压向第一节点提供可调节的第一伪电源电压，包括基于第一参考电压产生第一伪电源电压和来自第一个节点的反馈。在该实施例中，电压模式驱动器电路包括被配置为选择性地将第一节点或第二节点之一耦合到第一差分输出端和第一节点或第二节点中的不同一个到第二差分输出终端的开关电路在数据信号上。在该实施例中，电压模式驱动器电路包括电流模式加重驱动器，其被配置为选择性地将第一差分输出端或第二差分输出端中的一个耦合到第一组一个或多个电流源和第一差分输出端子或第二差分输出端子连接到基于一个或多个强调信号的一个或多个电流源的第二组。

5. 发明申请

US20160019029A1 Method and Apparatus for Randomizer 有权
标题翻译：随机机的方法和装置
公开(公告)号：US20160019029A1
公开(公告)日：2016-01-21
申请号：US14839576
申请日：2015-08-28
申请人： MoSys, Inc.
发明人： Michael J. MILLER , Michael J. MORRISON , Jay B. PATEL
IPC分类号： G06F7/58
CPC分类号： G06F7/582
摘要： A Method and Apparatus for Randomizer has been disclosed. In one implementation a sequence of randomized connections then exclusive-OR operations and then an adder produce a randomized output.
摘要翻译：已经公开了一种随机器的方法和装置。在一个实现中，随机连接序列然后是异或运算，然后是加法器产生随机输出。

6. 发明申请

US20130332681A1 MEMORY SYSTEM INCLUDING VARIABLE WRITE BURST AND BROADCAST COMMAND SCHEDULING 有权
标题翻译：存储系统，包括可变写波峰和广播命令调度
公开(公告)号：US20130332681A1
公开(公告)日：2013-12-12
申请号：US13911218
申请日：2013-06-06
申请人： MoSys, Inc.
发明人： Michael J. Miller , Michael J. Morrison , Jay B. Patel
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0644 , G06F9/3004 , G06F13/1626 , G06F13/1642 , G06F13/28
摘要： A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a memory write burst command having a first frame that includes a corresponding opcode positioned in one of a first command slot or a second command slot. The memory write burst command may also include a number of subsequent frames for conveying a data payload, as specified for example, by the opcode. The control unit may be configured to generate a number of concurrent sequential memory write operations to the memory in response to receiving the memory write burst command.
摘要翻译：系统包括主机设备，其可以被配置为向系统存储器发起存储器请求。该系统还包括可被配置为接收存储器请求并且将存储器请求格式化成通过存储器接口传送到存储器设备的存储器事务的存储器控制器。存储器事务包括具有第一帧的存储器写突发命令，该第一帧包括位于第一命令槽或第二命令槽之一中的对应操作码。存储器写突发命令还可以包括用于传送例如由操作码指定的数据有效载荷的多个后续帧。控制单元可以被配置为响应于接收到存储器写入突发命令而向存储器生成多个并行顺序存储器写入操作。

7. 发明申请

US20220114103A1 GRAPH MEMORY ENGINE 有权
公开(公告)号：US20220114103A1
公开(公告)日：2022-04-14
申请号：US17378647
申请日：2021-07-16
申请人： MoSys, Inc.
发明人： Michael J. Miller
IPC分类号： G06F12/0875
摘要： A system, method, and apparatus for graph memory. In one embodiment, the method includes: traversing program instructions disposed in an associative memory for operating a computer, the method comprising: receiving input data to be processed; identifying a next instruction to be fetched in the memory for processing the input data via: receiving a current node ID of a current state; performing a computational test on the input data resulting in a computed value; generating a search key by combining at least a portion of the computed edge value with the current node ID; and accessing the next instruction in associative memory via the search key.

8. 发明授权

US10114558B2 Integrated main memory and coprocessor with low latency 有权
公开(公告)号：US10114558B2
公开(公告)日：2018-10-30
申请号：US15898659
申请日：2018-02-18
申请人： MoSys, Inc.
发明人： Michael J. Miller , Jay B Patel , Michael J Morrison
IPC分类号： G06F3/06 , G06F9/38 , G06F12/00 , H04L29/12 , H04L29/08 , G06F12/0875 , G06F12/0895
摘要： System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.

9. 发明申请

US20150244381A9 DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE 审中-公开
标题翻译：具有双循环滤波器的延迟环路用于快速响应和宽频率和延迟范围
公开(公告)号：US20150244381A9
公开(公告)日：2015-08-27
申请号：US14231730
申请日：2014-03-31
申请人： MoSys, Inc.
发明人： Prashant Choudhary , Aldo Bottelli , Charles W. Boecker
IPC分类号： H03L7/07
CPC分类号： H03L1/00 , H03L7/07 , H03L7/08 , H03L7/0816 , H04L7/0338
摘要： A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
摘要翻译：延迟锁定环路包括用于控制延迟锁定环路中的延迟元件的两个反馈回路。第一反馈回路包括反馈电路，用于基于延迟锁定环路的输入时钟信号与由延迟锁定环路产生的输出时钟信号之间的相位差产生指示延迟调整的反馈信号。第二反馈回路包括功率调节器，其通过使用反馈信号作为参考来调节电源来产生调节信号。延迟锁定环路还包括包括电阻 - 电容网络的可变延迟电路。可变延迟电路基于反馈信号控制电阻 - 电容网络中的电容，并根据调节信号控制电阻 - 电容网络的电阻。以这种方式，可变延迟电路通过基于反馈信号和调节信号两者延迟输入时钟信号来产生输出时钟信号。

10. 发明授权

US09030894B2 Hierarchical multi-bank multi-port memory organization 有权
标题翻译：分层多行多端口内存组织
公开(公告)号：US09030894B2
公开(公告)日：2015-05-12
申请号：US13972798
申请日：2013-08-21
申请人： MoSys, Inc.
发明人： Richard S. Roy , Dipak Kumar Sikdar
IPC分类号： G11C7/00 , G11C11/413 , G11C7/10
CPC分类号： G11C7/00 , G11C7/1075 , G11C11/413
摘要： A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.
摘要翻译：存储器系统包括多个（N）个存储体和多个（M）端口，其中N大于或等于M.存储器组中的每一个耦合到每个端口。在每个端口上同时发送访问请求。然而，每个同时访问请求指定了不同的存储体。每个存储器监视端口上的访问请求，并确定任何访问请求是否指定存储体。在确定访问请求指定存储体时，存储体执行对单端口存储单元阵列的访问。在多个存储体中执行同时访问，提供等于一个存储体的带宽乘以端口数的带宽。可以提供额外的层次级别，这允许以最小的面积开销进一步增加同时访问的端口的数量。

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