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1. 发明授权

US09087595B2 Shielding 2-cycle half-page read and program schemes for advanced NAND flash design 有权
标题翻译：屏蔽用于高级NAND闪存设计的2周期半页读取和编程方案
公开(公告)号：US09087595B2
公开(公告)日：2015-07-21
申请号：US13867051
申请日：2013-04-20
申请人： Aplus Flash Technology, Inc
发明人： Peter Wung Lee
IPC分类号： G11C16/26 , G11C16/04 , G11C11/56 , G11C16/24 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/0408 , G11C16/0483 , G11C16/24 , G11C16/3427
摘要： The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period.
摘要翻译：本发明通过将整个NAND阵列位线（BL）分成奇数BL组和偶数BL组来提供双周期半页读取方案。在奇数（偶数）-BL组中的NAND单元的半平面读取期间，半平面偶数（奇数）-BL组用作屏蔽BL以在奇数（偶数）-BL字符串读数上保护，半页读取操作基本可靠，不受BL耦合噪声影响。此外，每个半页读取操作优选地被分为3个周期：第一个是所选WL的偏置条件建立周期和剩余的控制信号; 第二个是所有BL的预充电期; 第三个是半页闪存数据传感时段。

2. 发明授权

US08971113B2 Pseudo-8T NVSRAM cell with a charge-follower 有权
标题翻译：带有充电跟随器的伪8T NVSRAM单元
公开(公告)号：US08971113B2
公开(公告)日：2015-03-03
申请号：US14064220
申请日：2013-10-28
申请人： Aplus Flash Technology, Inc
发明人： Peter Wung Lee
IPC分类号： G11C11/34 , G11C14/00
CPC分类号： G11C14/0063
摘要： The present invention discloses a 10T NVSRAM cell with a 6T SRAM cell with 4T Flash cell with one dedicated Flash-based Charger. In addition, a Pseudo-8T NVSRAM cell with a shared Flash-based Charger between two adjacent 8T NVSRAM cells at top and bottom in cell layout is also disclosed to further reduce cell size by 20%. As opposed to the prior art of 12T NVSRAM cell, the Store operation of the above two preferred embodiments use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower ensured by the Flash-based Charger to obtain the final ΔVQ-QB>0.2V at Q and QB nodes of each SRAM cell to cover all the mismatched of parasitic capacitance in flash cell devices and layout for a reliable amplification by ramping up SRAM's VDD line and ramping down SRAM's VSS line.
摘要翻译：本发明公开了一种具有6T SRAM单元的10T NVSRAM单元，具有4T闪存单元和一个专用的基于闪存的充电器。此外，还公开了在单元格布局的顶部和底部的两个相邻的8T NVSRAM单元之间具有共享的基于闪存的充电器的伪8T NVSRAM单元，以进一步将单元大小减小20％。与12T NVSRAM单元的现有技术相反，上述两个优选实施例的存储操作使用具有闪存单元的DRAM状电荷感测方案，其被配置为由基于闪存的充电器确保的电压跟随器以获得最终的＆Dgr; 每个SRAM单元的Q和QB节点的VQ-QB> 0.2V，以覆盖闪存单元器件中的所有寄生电容失配，并通过升高SRAM的VDD线并降低SRAM的VSS线来布置可靠的放大。

3. 发明授权

US09443579B2 VSL-based VT-compensation and analog program scheme for NAND array without CSL 有权
标题翻译：基于VSL的VT补偿和无CSL的NAND阵列的模拟程序方案
公开(公告)号：US09443579B2
公开(公告)日：2016-09-13
申请号：US14828427
申请日：2015-08-17
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C5/02 , G11C11/56 , G11C16/10 , G11C16/26 , G11C16/04 , G11C16/34 , G11C7/18 , G11C16/08
CPC分类号： G11C11/5635 , G11C7/18 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C16/3459 , G11C2207/2245 , G11C2211/5641
摘要： A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) with full BL-shielding without wasting extra silicon area and without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding to perform concurrent ABL, AnP and Alt-WL program under multi-passes program schemes with LBL program voltage compensations and half-BL Odd/Even program-verify and read operations with individual VSL-based Vt-compensation to mitigate high WL-WL and BL-BL coupling effects.
摘要翻译： YUKAI NAND阵列包括与分层全局/局部位线（GBL / LBL）相关联的所有TLC和混合TLC + SLC存储器单元的多个串，每个串与一个LBL相关联并且具有相邻的LBL作为专用本地源极线（LSL ）具有完全的BL屏蔽，而不浪费额外的硅面积，没有通用的源极线连接所有的串。每个LBL与通过插入每个串中的一对虚拟单元选择的奇数或偶数字符串进行交织关联，并且用作具有完全BL屏蔽的一个片上PCACHE寄存器，以执行并行ABL，AnP和Alt-WL 在具有LBL程序电压补偿和半BL奇偶校验和读取操作的多通程序方案下使用单独的基于VSL的Vt补偿来减轻WL-WL和BL-BL耦合效应。

4. 发明授权

US09001545B2 NOR-based BCAM/TCAM cell and array with NAND scalability 有权
标题翻译：基于NOR的BCAM / TCAM单元和具有NAND可扩展性的阵列
公开(公告)号：US09001545B2
公开(公告)日：2015-04-07
申请号：US14016089
申请日：2013-08-31
申请人： Aplus Flash Technology, Inc.
发明人： Peter Wung Lee
IPC分类号： G11C15/00 , G11C15/04 , G11C16/04
CPC分类号： G11C15/046 , G11C15/04 , G11C16/0483
摘要： This invention discloses a 2T-string NOR-based CAM logic cell comprising two physical NAND cells connected in series with two horizontal WLs and one vertical BL and one vertical SL. Additionally, a sector of NOR-based CAM logic cell array is configured with N vertical cell strings each including M 2T-string NOR-based CAM logic cells connected in parallel sharing a local vertical SL and one dedicated vertical ML as an Operand word vertical page. Each 2T-string NOR-based CAM logic cell can be either a binary or ternary CAM cell associated with two or three physical states assigned to NAND cells' Vt levels for defining CAM logic states. Logic match of M-logic-bit inputs is found for at least one vertical page if the corresponding M 2T-string NOR-based CAM logic cells are in non-conduction state, providing M times faster Compare performance over the NAND-based CAM and 2 time faster than SRAM-based CAM.
摘要翻译：本发明公开了一种基于2T串NOR的CAM逻辑单元，其包括与两个水平WL和一个垂直BL和一个垂直SL串联连接的两个物理NAND单元。另外，NOR型CAM逻辑单元阵列的扇区被配置有N个垂直单元串，每个垂直单元串包括并行连接的M 2T串NOR基CAM逻辑单元，共享一个本地垂直SL和一个专用垂直ML作为操作数字垂直页。每个2T字符串的基于NOR的CAM逻辑单元可以是与分配给NAND单元的Vt级别的两个或三个物理状态相关联的二进制或三元CAM单元，用于定义CAM逻辑状态。如果对应的M 2T串NOR型CAM逻辑单元处于非导通状态，则可以为至少一个垂直页面找到M逻辑位输入的逻辑匹配，提供比基于NAND的CAM提供M倍快比较性能，比基于SRAM的CAM快2倍。

5. 发明授权

US09595319B2 Partial/full array/block erase for 2D/3D hierarchical NAND 有权
标题翻译： 2D / 3D分层NAND的部分/全阵列/块擦除
公开(公告)号：US09595319B2
公开(公告)日：2017-03-14
申请号：US15137284
申请日：2016-04-25
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C11/56 , G11C16/04 , G11C16/08 , H01L27/115
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/3418 , G11C16/3445 , H01L27/11556 , H01L27/11582
摘要： A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid at a level below a plurality of broken or non-broken global bit lines (GBLs) connected to Page Buffer. Each LG group includes multiple blocks and connects an independent power supply line to each of the plurality of LBLs. Each block including N-bit 2D/3D NAND strings each with S cells connected in series and terminated by two string-select devices and coupled to a common source line. In particular, random-size partial-block WLs are selected from each block of randomly selected LG groups of one plane of the 2D/3D NAND array for erase at the same time with border WLs being optionally preread and program into another plane of the 2D/3D NAND array or optionally saved off-chip and wrote back for data security.
摘要翻译：一种新颖的2D / 3D分层BL NAND阵列，其独立的基板上具有至少一个平面，包括分别与多个局部位线（LBL）相关联的多个LG组，所述多个局部位线布置在低于多个破碎或非断开全局连接到页面缓冲区的位线（GBL）。每个LG组包括多个块，并且将独立电源线连接到多个LBL中的每一个。每个块包括N位2D / 3D NAND串，每个NAND串都具有串联连接的S个单元，并由两个串选择器件终止并耦合到公共源极线。特别地，随机大小的部分块WL从2D / 3D NAND阵列的一个平面的随机选择的LG组的每个块中选择同时进行擦除，边界WL可选地被预读，并且编程到2D的另一个平面 / 3D NAND阵列或可选地保存在片外，并回写数据安全。

6. 发明授权

US09524773B2 Multi-task concurrent/pipeline NAND operations on all planes 有权
公开(公告)号：US09524773B2
公开(公告)日：2016-12-20
申请号：US14966894
申请日：2015-12-11
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C11/56 , G11C16/34 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C7/10 , H01L27/115
CPC分类号： G11C11/5635 , G11C7/1039 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3445 , G11C16/3459 , H01L27/1157 , H01L27/11582
摘要： This invention provides a 2-level BL-hierarchical NAND memory architecture and associated concurrent operations applicable to both 2D and 3D HiNAND2 memory arrays. New Latch designs in Block-decoder and Segment-decoder with one common dedicated metal0 power line per one 2N-bit dynamic page buffer (DPB) formed in corresponding 2N broken-LBL metal1 line capacitors for Program and per one 2N-bit Segment DPB formed in corresponding 2N local LBL metal1 line capacitors for Read are provided for performing concurrent and pipeline operations of multiple-WL Program, Read, Erase-Verify, and Program-Verify in dispersed Blocks in a same or multiple different NAND planes with much enhanced array flexibility and multiple-fold performance improvements.

7. 发明授权

US09183940B2 Low disturbance, power-consumption, and latency in NAND read and program-verify operations 有权
标题翻译： NAND读取和程序验证操作中的低干扰，功耗和延迟
公开(公告)号：US09183940B2
公开(公告)日：2015-11-10
申请号：US14283209
申请日：2014-05-20
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C16/04 , G11C16/26 , G11C16/10 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5641
摘要： A HiNAND array with a hierarchical-BL scheme configured to divide a large global bit line (GBL) capacitance into J number of small local bit line (LBL) capacitances for reducing bit line precharge voltage and discharge time to achieve faster Read and Program-Verify speed, lower power consumption, lower latency, and lower word line disturbance for a reliable DRAM-like latch sensing. A reduced precharge voltage can be increased by M-fold (M≧2) using a Multiplier between each bitline and each Latch sense amplifier (SA). Between each Multiplier and each Latch SA, there is a Connector with two optional designs for either fully passing a sense voltage to the Latch SA with a same-polarity and value or reversing the polarity the sensing voltage with additional amplification. The Latch SA is configured to transfer stored threshold states of a memory cell into a bit of a page buffer.
摘要翻译：具有分层BL方案的HiNAND阵列被配置为将大的全局位线（GBL）电容分成J个小的局部位线（LBL）电容，以减少位线预充电电压和放电时间，以实现更快的读取和编程验证速度，更低的功耗，更低的延迟和更低的字线干扰，以实现可靠的类DRAM锁存检测。使用每个位线和每个锁存读出放大器（SA）之间的乘数，可以减小预充电电压M倍（M≥2）。在每个乘法器和每个锁存器SA之间，具有两个可选设计的连接器，用于将具有相同极性和值的Latch SA的感测电压完全传递，或者通过附加放大来反转感测电压的极性。 Latch SA被配置为将存储器单元的存储的阈值状态传送到页缓冲器的位中。

8. 发明授权

US09001583B2 On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation 有权
标题翻译：作为NVSRAM自动存储操作的第二个备用电源的片上HV和LV电容
公开(公告)号：US09001583B2
公开(公告)日：2015-04-07
申请号：US14053549
申请日：2013-10-14
申请人： Aplus Flash Technology, Inc
发明人： Peter Wung Lee , Hsing-Ya Tsao
IPC分类号： G11C11/34 , G11C16/30 , G11C5/14 , G11C14/00 , G11C16/12 , G11C16/22
CPC分类号： G11C16/30 , G11C5/141 , G11C14/0063 , G11C16/12 , G11C16/22
摘要： Two on-chip capacitors including one HV capacitor VPPcap and one LV VCC capacitor VCCcap are built over a NVSRAM memory chip as a back-up second power supplies for each NVSRAM cell, regardless of 1-poly, 2-poly, PMOS or NMOS flash cell structures therein. The on-chip HV and LV capacitors are preferably made from one or more MIM or MIP layers for achieving required capacitance. A simplified VCC power system circuit without a need of a State machine designed for performing only one NVSRAM Program operation without Erase operations is proposed for initiating NVSRAM's Auto-Store operation without using any off-chip Vbat and Vcap. During the Auto-Store operation, all HV pumps and oscillators associated with the two on-chip capacitors are shut off once VCC voltage drop is detected by a VCC detector to be below 80% of regular VDD level.
摘要翻译：两个片上电容器包括一个HV电容器VPPcap和一个LV VCC电容器VCCcap，构成NVSRAM存储器芯片，作为每个NVSRAM单元的备用第二个电源，无论1-poly，2-poly，PMOS或NMOS闪存其中的细胞结构。片上HV和LV电容器优选地由用于实现所需电容的一个或多个MIM或MIP层制成。提出了一种简化的VCC电源系统电路，不需要设计用于仅执行一个NVSRAM编程操作而不进行擦除操作的状态机，用于启动NVSRAM的自动存储操作，而不使用任何片外Vbat和Vcap。在自动存储操作期间，一旦VCC检测器检测到VCC电压降低到正常VDD电平的80％，则与两个片上电容器相关的所有HV泵和振荡器都将被关闭。

9. 发明授权

US09666286B2 Self-timed SLC NAND pipeline and concurrent program without verification 有权
公开(公告)号：US09666286B2
公开(公告)日：2017-05-30
申请号：US14859237
申请日：2015-09-18
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C16/08 , G11C16/26 , G11C16/34 , G11C16/32
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32 , G11C16/3459
摘要： A hierarchical-GBL/LBL NAND array with a plurality of LG and MG groups in either orthogonal BL/CSL scheme or parallel BL/SL scheme including a plurality of block-decoders with a shared self-timed delay control circuit and a plurality of fully-shielding dynamic CACHE registers made of 2 local broken metal lines within the array and DRAM-like SA is provided. Each DCR capacitor is flexibly expandable by connecting multiple CLGs made by the local broken metal lines of the LGs to form a CMG of a larger MG. Based on the NAND array, multiple randomly selected WLs in multiple random blocks within multiple random LGs within one MG can be selected on basis of one WL per block per LG for performing an ABL pipeline and concurrent SLC program without verification, and on basis of one WL per block per MG for performing an ABL-like or HBL pipeline and concurrent SLC read.

10. 发明授权

US09530492B2 NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations 有权
标题翻译：用于多WL和全BL同时擦除，擦除验证，程序，程序验证和读取操作的NAND阵列高性能BL结构
公开(公告)号：US09530492B2
公开(公告)日：2016-12-27
申请号：US14953384
申请日：2015-11-29
申请人： Peter Wung Lee
发明人： Peter Wung Lee
IPC分类号： G11C16/04 , G11C11/56 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/06 , G11C16/14 , G11C16/24
CPC分类号： G11C11/5635 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3459 , G11C2211/5641
摘要： Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1 (top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metal0 power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple-WL and All-BL Program and Program-Verify operation with reduced program current for highest program yield superior P/E cycles.
摘要翻译：提供了一些具有1级或2级破碎的BL级别结构的2D和3D HiNAND闪存阵列，用于分散块中的Multiple Whole-WL和All-BL同时操作。全局位线（GBL）被划分为多个1（顶）级破碎金属2 GBL加上可选的较低级别的破碎金属1局部位线（LBL）。可以通过水平金属电源线LBL选择性地提供高于Vdd的优选Vinhibit电源，以对所选择的破坏的GBL / LBL充电，也可以经由串源线选择性地放电。用于NAND电池数据传感的破碎GBL / LBL电容器的充电和放电的电荷共享技术用于读取和验证操作，具有降低的功耗和延迟。用于恢复存储在破碎的GBL / LBL电容器中的所需程序数据的恢复技术用于多WL和全BL程序和程序验证操作，具有减少的程序电流，用于最高程序产生优异的P / E周期。

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