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1. 发明授权

US10014876B1 High speed buffering for time-interleaved ADCS with reduced ISI and increased voltage gain 有权
公开(公告)号：US10014876B1
公开(公告)日：2018-07-03
申请号：US15451194
申请日：2017-03-06
申请人： Applied Micro Circuits Corporation
发明人： Nanda Govind Jayaraman
IPC分类号： H03M1/06 , H03M1/12 , H03M1/38
CPC分类号： H03M1/38 , H03M1/1215 , H03M1/1245
摘要： System and method of buffering sampled signals in a time-interleaved analog-to-digital converter (ADC). When the input voltage to the buffer varies to a different level, a constant reset voltage is supplied to the buffer output that drives a large capacitive load, e.g., composed of an array of sub-ADCs. The reset voltage functions to remove the capacitive effect from a previous output value on the load. As a result, the buffer can buffer the input for the load without introducing intersymbol interference (ISI). A reset switch can be used to control the supply of the reset voltage to the buffer output according to a predetermined clock signal. The reset voltage may be the common mode potential in a differential source follower in the buffer. An additional voltage gain can be advantageously achieved by the buffer with a gain factor being independent of the load capacitance.

2. 发明授权

US09991907B1 Concatenates of an E8 lattice with binary and non binary codes 有权
公开(公告)号：US09991907B1
公开(公告)日：2018-06-05
申请号：US14466361
申请日：2014-08-22
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Dariush Dabiri
IPC分类号： H03M13/00 , H03M13/11 , H03M13/15 , H03M13/19 , H03M13/25 , H03M13/29 , H04L1/00
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/134 , H03M13/152 , H03M13/19 , H03M13/253 , H03M13/256 , H03M13/258 , H03M13/2909 , H03M13/2957 , H03M13/3916 , H03M13/616 , H03M13/63 , H04B1/38 , H04B3/02 , H04L1/0041 , H04L1/0045 , H04L1/0058 , H04L1/0061 , H04L1/0067 , H04L5/14 , H04L5/1423 , H04L7/042 , H04L27/0002 , H04L27/3483
摘要： A transceiver architectures can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on concatenations of an E8 lattice having binary and non-binary codes. The data can be transmitted at a high speed according to the constellation with an embedded E8 lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.

3. 发明申请

US20180123776A1 MITIGATING INTERACTION BETWEEN ADAPTIVE EQUALIZATION AND TIMING RECOVERY 审中-公开
公开(公告)号：US20180123776A1
公开(公告)日：2018-05-03
申请号：US15336435
申请日：2016-10-27
申请人： Applied Micro Circuits Corporation
发明人： Yehuda AZENKOT , Bart R. ZEYDEL
IPC分类号： H04L7/04 , H04L25/08 , H04L12/26 , H04B17/336
CPC分类号： H04L7/04 , H04B17/336 , H04L7/0025 , H04L7/0029 , H04L7/0037 , H04L7/0062 , H04L25/0307 , H04L25/03885 , H04L25/08 , H04L27/01 , H04L43/028
摘要： System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.

4. 发明授权

US09882709B2 Timing recovery with adaptive channel response estimation 有权
公开(公告)号：US09882709B2
公开(公告)日：2018-01-30
申请号：US15151154
申请日：2016-05-10
申请人： Applied Micro Circuits Corporation
发明人： Yehuda Azenkot , Bart R. Zeydel
IPC分类号： H04L7/00 , H04L7/033 , H04L25/03 , H04L7/04
CPC分类号： H04L7/04 , H04L7/0062 , H04L7/0087 , H04L7/0331 , H04L25/024 , H04L25/03019 , H04L25/03261 , H04L25/03292 , H04L25/03949 , H04L2025/03592 , H04L2025/03636
摘要： System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.

5. 发明授权

US09876007B1 MIMcap creation and utilization methodology 有权
公开(公告)号：US09876007B1
公开(公告)日：2018-01-23
申请号：US15149244
申请日：2016-05-09
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Ronen Cohen , Alfred Yeung , Ojas Dharia
IPC分类号： H01L21/8242 , H01L27/02 , H01L49/02 , H01L23/522 , H01L23/535 , G06F17/50
CPC分类号： H01L27/0288 , G06F17/5072 , G06F17/5077 , G06F17/5081 , H01L23/5223 , H01L23/535 , H01L27/0207 , H01L28/60
摘要： A metal-insulator-metal (MIM) capacitor design methodology and system substantially maximizes the benefits of including MIM capacitors in an integrated circuit design while substantially minimizing the negative impacts resulting from increased capacitance. A process analysis is performed on an integrated circuit design to determine a metal layer that is likely to be most adversely affected by the presence of MIM capacitor cells. The MIM capacitor cells are then designed to have specific sizes and orientations based on results of the process analysis, taking the most affected metal layer into consideration. Finally, the MIM capacitor cells are placed at selected locations on the die in an algorithmic fashion in order to satisfy a design target of maximizing coverage area while avoiding interference with signal paths and critical or sensitive components.

6. 发明申请

US20170373827A1 RESOLVING INTERACTION BETWEEN CHANNEL ESTIMATION AND TIMING RECOVERY 有权
公开(公告)号：US20170373827A1
公开(公告)日：2017-12-28
申请号：US15191229
申请日：2016-06-23
申请人： Applied Micro Circuits Corporation
发明人： Yehuda AZENKOT , Bart R. ZEYDEL
IPC分类号： H04L7/04 , H04L7/033 , H04L7/00
CPC分类号： H04L7/04 , H04L7/0062 , H04L7/0087 , H04L7/0331 , H04L25/03
摘要： System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

7. 发明申请

US20170331619A1 TIMING RECOVERY WITH ADAPTIVE CHANNEL RESPONSE ESTIMATION 有权
公开(公告)号：US20170331619A1
公开(公告)日：2017-11-16
申请号：US15151154
申请日：2016-05-10
申请人： Applied Micro Circuits Corporation
发明人： Yehuda AZENKOT , Bart R. ZEYDEL
IPC分类号： H04L7/04 , H04L25/03 , H04L7/00 , H04L7/033
CPC分类号： H04L7/04 , H04L7/0062 , H04L7/0087 , H04L7/0331 , H04L25/024 , H04L25/03019 , H04L25/03261 , H04L25/03292 , H04L25/03949 , H04L2025/03592 , H04L2025/03636
摘要： System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.

8. 发明授权

US09720830B2 Systems and methods facilitating reduced latency via stashing in system on chips 有权
公开(公告)号：US09720830B2
公开(公告)日：2017-08-01
申请号：US14796167
申请日：2015-07-10
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Millind Mittal
IPC分类号： G06F12/00 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875
CPC分类号： G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2212/1024 , G06F2212/251 , G06F2212/452 , G06F2212/602
摘要： Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.

9. 发明申请

US20170163380A1 HIGH SPEED ADD-COMPARE-SELECT FOR VITERBI DECODER 有权
公开(公告)号：US20170163380A1
公开(公告)日：2017-06-08
申请号：US14961228
申请日：2015-12-07
申请人： Applied Micro Circuits Corporation
发明人： Yehuda AZENKOT , Bart ZEYDEL
IPC分类号： H04L1/00
CPC分类号： H04L1/0054 , H03M13/4107 , H03M13/6502
摘要： System and method of comparing-selecting state metric values for high speed. Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select-control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.

10. 发明授权

US09588923B2 Flow pinning in a server on a chip 有权
标题翻译：在芯片上的服务器中流动锁定
公开(公告)号：US09588923B2
公开(公告)日：2017-03-07
申请号：US14162903
申请日：2014-01-24
申请人： APPLIED MICRO CIRCUITS CORPORATION
发明人： Keyur Chudgar , Kumar Sankaran
IPC分类号： G06F13/24 , G06F13/38
CPC分类号： G06F13/385
摘要： Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.
摘要翻译：各种实施例提供了芯片上的系统或执行流锁定的芯片上的系统，其中分组或分组流入队列到特定队列，其中每个队列与多处理器/多核系统中的相应核相关联或服务器在芯片上。对于分配给特定处理器的每个数据包流或流，芯片上的服务器可以并行地从同一个以太网接口的多个流处理和进入来自多个队列的数据包。每个队列可以向其分配的处理器发出中断，从而允许每个处理器同时从其各自的队列接收数据包。因此，通过为不同流并行接收和处理数据包，从而增加分组处理速度。

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