专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09207971B2 Data parallel computing on multiple processors 有权
标题翻译：多处理器上的数据并行计算
公开(公告)号：US09207971B2
公开(公告)日：2015-12-08
申请号：US13614975
申请日：2012-09-13
申请人： Aaftab Munshi , Jeremy Sandmel
发明人： Aaftab Munshi , Jeremy Sandmel
IPC分类号： G06F9/54 , G06F9/48 , G06F9/50
CPC分类号： G06F9/5044 , G06F9/4843 , G06F2209/5018
摘要： A method and an apparatus that allocate one or more physical compute devices such as CPUs or GPUs attached to a host processing unit running an application for executing one or more threads of the application are described. The allocation may be based on data representing a processing capability requirement from the application for executing an executable in the one or more threads. A compute device identifier may be associated with the allocated physical compute devices to schedule and execute the executable in the one or more threads concurrently in one or more of the allocated physical compute devices concurrently.
摘要翻译：描述分配一个或多个物理计算设备（诸如连接到运行用于执行应用的一个或多个线程的应用的主机处理单元的CPU或GPU）的方法和装置。分配可以基于表示来自用于在一个或多个线程中执行可执行程序的应用程序的处理能力要求的数据。计算设备标识符可以与所分配的物理计算设备相关联，以在一个或多个所分配的物理计算设备中同时调度和执行一个或多个线程中的可执行文件。

2. 发明授权

US08276164B2 Data parallel computing on multiple processors 有权
标题翻译：多处理器上的数据并行计算
公开(公告)号：US08276164B2
公开(公告)日：2012-09-25
申请号：US11800185
申请日：2007-05-03
申请人： Aaftab Munshi , Jeremy Sandmel
发明人： Aaftab Munshi , Jeremy Sandmel
IPC分类号： G06F9/06
CPC分类号： G06F9/5044 , G06F9/4843 , G06F2209/5018
摘要： A method and an apparatus that allocate one or more physical compute devices such as CPUs or GPUs attached to a host processing unit running an application for executing one or more threads of the application are described. The allocation may be based on data representing a processing capability requirement from the application for executing an executable in the one or more threads. A compute device identifier may be associated with the allocated physical compute devices to schedule and execute the executable in the one or more threads concurrently in one or more of the allocated physical compute devices concurrently.
摘要翻译：描述分配一个或多个物理计算设备（诸如连接到运行用于执行应用的一个或多个线程的应用的主机处理单元的CPU或GPU）的方法和装置。分配可以基于表示来自用于在一个或多个线程中执行可执行程序的应用程序的处理能力要求的数据。计算设备标识符可以与所分配的物理计算设备相关联，以在一个或多个所分配的物理计算设备中同时调度和执行一个或多个线程中的可执行文件。

3. 发明申请

US20060139351A1 Object visibility control for ray tracing 有权
公开(公告)号：US20060139351A1
公开(公告)日：2006-06-29
申请号：US11244417
申请日：2005-10-04
申请人： Aaftab Munshi
发明人： Aaftab Munshi
IPC分类号： G06T15/50
CPC分类号： G06T15/40 , G06T15/06
摘要： A computer graphics method and apparatus allows designer control over the rendering of objects and scenes, in a rendering system using ray tracing for example. A modeling system is adapted to accept rules for controlling how certain objects affect the appearance of certain other objects. In a ray tracing implementation, rules are specified by ray type and can be specified as either “including” all but certain objects or “excluding” specific objects for any given object. A rendering system extracts these rules from a bytestream or other input including other graphics data and instructions, and populates lists for internal use by other components of the rendering system. A ray tracer in the rendering system is adapted to consult the list when performing ray tracing, so as to enforce the rendering control specified by the content creator when the objects and scene are rendered.

4. 发明申请

US20050024370A1 Fully associative texture cache having content addressable memory and method for use thereof 有权
标题翻译：具有内容可寻址存储器的完全关联纹理缓存及其使用方法
公开(公告)号：US20050024370A1
公开(公告)日：2005-02-03
申请号：US10931375
申请日：2004-08-31
申请人： Aaftab Munshi
发明人： Aaftab Munshi
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00 , G09G5/36
CPC分类号： G06T15/005 , G06T1/60
摘要： A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address. The cache memory includes first and second memories coupled together by a plurality of activation lines. The first memory has a corresponding plurality of address detection units to store addresses and provide activation signals in response to receiving a matching address. The second memory includes a corresponding plurality of data storage locations. Each data storage location is coupled to a respective one of the plurality of address storage locations by a respective activation line to provide graphics data in response to receiving an activation signal from the respective address storage location.
摘要翻译：图形处理系统包括耦合到图形处理器的高速缓存存储器电路和用于根据相应地址存储图形数据的地址和数据总线。高速缓冲存储器包括通过多个激活线耦合在一起的第一和第二存储器。第一存储器具有相应的多个地址检测单元，用于存储地址并响应于接收匹配地址而提供激活信号。第二存储器包括对应的多个数据存储位置。每个数据存储位置通过相应的激活线耦合到多个地址存储位置中的相应一个，以响应于从相应的地址存储位置接收激活信号来提供图形数据。

5. 发明授权

US06784892B1 Fully associative texture cache having content addressable memory and method for use thereof 失效
标题翻译：具有内容可寻址存储器的完全关联纹理缓存及其使用方法
公开(公告)号：US06784892B1
公开(公告)日：2004-08-31
申请号：US09684168
申请日：2000-10-05
申请人： Aaftab Munshi
发明人： Aaftab Munshi
IPC分类号： G09G536
CPC分类号： G06T15/005 , G06T1/60
摘要： A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address. The cache memory includes first and second memories coupled together by a plurality of activation lines. The first memory has a corresponding plurality of address detection units to store addresses and provide activation signals in response to receiving a matching address. The second memory includes a corresponding plurality of data storage locations. Each data storage location is coupled to a respective one of the plurality of address storage locations by a respective activation line to provide graphics data in response to receiving an activation signal from the respective address storage location.
摘要翻译：图形处理系统包括耦合到图形处理器的高速缓存存储器电路和用于根据相应地址存储图形数据的地址和数据总线。高速缓冲存储器包括通过多个激活线耦合在一起的第一和第二存储器。第一存储器具有相应的多个地址检测单元，用于存储地址并响应于接收匹配地址而提供激活信号。第二存储器包括对应的多个数据存储位置。每个数据存储位置通过相应的激活线耦合到多个地址存储位置中的相应一个，以响应于从相应的地址存储位置接收激活信号来提供图形数据。

6. 发明授权

US06678755B1 Method and apparatus for appending memory commands during a direct memory access operation 有权
标题翻译：在直接存储器访问操作期间附加存储器命令的方法和装置
公开(公告)号：US06678755B1
公开(公告)日：2004-01-13
申请号：US09608544
申请日：2000-06-30
申请人： James R. Peterson , Aaftab Munshi , Mohammed Sriti
发明人： James R. Peterson , Aaftab Munshi , Mohammed Sriti
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： A direct memory access (DMA) controller for controlling memory access operations in a memory. During a memory access operation, the DMA controller executes a chain of DMA commands stored in a memory and having a respective address. The DMA controller can enter a self-linking mode where additional DMA commands can be appended to the end of the command chain without terminating the memory access operation, regardless of whether the last DMA command of the command chain has been executed by the DMA controller. The self-linking mode is entered when a link-address provided by the last DMA command matches a code. The code to cause the DMA controller to enter the self-linking mode may be a link address which points to the last executed DMA command, or alternatively, a predetermined bit pattern. The DMA controller exits the self-linking command and continues the memory access operation upon detecting a new link address for a new DMA command that is to be appended to the command chain. The new link address may be detected by having the DMA controller periodically check the link address of the last executed DMA command.
摘要翻译：用于控制存储器中的存储器访问操作的直接存储器访问（DMA）控制器。在存储器访问操作期间，DMA控制器执行存储在存储器中并具有相应地址的一系列DMA命令。 DMA控制器可以进入自链接模式，其中附加的DMA命令可以附加到命令链的末尾而不终止存储器访问操作，而不管命令链的最后一个DMA命令是否由DMA控制器执行。当最后一个DMA命令提供的链接地址匹配一个代码时，输入自链接模式。导致DMA控制器进入自链接模式的代码可以是指向最后执行的DMA命令的链接地址，或者备选地是预定位模式。 DMA控制器退出自链接命令，并在检测到要附加到命令链的新DMA命令的新链接地址时继续存储器访问操作。可以通过使DMA控制器周期性地检查最后执行的DMA命令的链路地址来检测新的链路地址。

7. 发明授权

US09304834B2 Parallel runtime execution on multiple processors 有权
公开(公告)号：US09304834B2
公开(公告)日：2016-04-05
申请号：US13615473
申请日：2012-09-13
申请人： Aaftab Munshi , Jeremy Sandmel
发明人： Aaftab Munshi , Jeremy Sandmel
IPC分类号： G06F9/44 , G06F9/48 , G06F9/54 , G06F9/445 , G06F9/45 , G06F9/50
CPC分类号： G06F9/445 , G06F8/41 , G06F8/447 , G06F9/44542 , G06F9/4843 , G06F9/5044 , G06F9/541
摘要： A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or GPUs concurrently are described. One or more executables are compiled online from a source having an existing executable for a type of physical compute devices different from the one or more physical compute devices. Dependency relations among elements corresponding to scheduled executables are determined to select an executable to be executed by a plurality of threads concurrently in more than one of the physical compute devices. A thread initialized for executing an executable in a GPU of the physical compute devices are initialized for execution in another CPU of the physical compute devices if the GPU is busy with graphics processing threads.

8. 发明申请

US20130007774A1 DATA PARALLEL COMPUTING ON MULTIPLE PROCESSORS 审中-公开
标题翻译：数据并行计算在多个处理器上
公开(公告)号：US20130007774A1
公开(公告)日：2013-01-03
申请号：US13614975
申请日：2012-09-13
申请人： Aaftab Munshi , Jeremy Sandmel
发明人： Aaftab Munshi , Jeremy Sandmel
IPC分类号： G06F9/46 , G06F15/76
CPC分类号： G06F9/5044 , G06F9/4843 , G06F2209/5018
摘要： A method and an apparatus that allocate one or more physical compute devices such as CPUs or GPUs attached to a host processing unit running an application for executing one or more threads of the application are described. The allocation may be based on data representing a processing capability requirement from the application for executing an executable in the one or more threads. A compute device identifier may be associated with the allocated physical compute devices to schedule and execute the executable in the one or more threads concurrently in one or more of the allocated physical compute devices concurrently.
摘要翻译：描述分配一个或多个物理计算设备（诸如连接到运行用于执行应用的一个或多个线程的应用的主机处理单元的CPU或GPU）的方法和装置。分配可以基于表示来自用于在一个或多个线程中执行可执行程序的应用程序的处理能力要求的数据。计算设备标识符可以与所分配的物理计算设备相关联，以在一个或多个所分配的物理计算设备中同时调度和执行一个或多个线程中的可执行文件。

9. 发明申请

US20060215914A1 Block-based image compression method and apparatus 有权
公开(公告)号：US20060215914A1
公开(公告)日：2006-09-28
申请号：US11090378
申请日：2005-03-25
申请人： Milivoje Aleksic , Aaftab Munshi , Charles Ogden
发明人： Milivoje Aleksic , Aaftab Munshi , Charles Ogden
IPC分类号： G06K9/36
CPC分类号： H04N19/94 , H04N19/124 , H04N19/186 , H04N19/42 , H04N19/426
摘要： A block-based image compression method and encoder/decoder circuit compresses a plurality of pixels having corresponding original color values and luminance values in a block according to different modes of operation. The encoding circuit includes a luminance-level-based representative color generator to generate representative color values for each of a plurality of luminance levels derived from the corresponding luminance levels to produce at least a block color offset value and a quantization value. According to mode zero, each of the pixels in the block is associated with one of the plurality of generated representative color values to generate error map values and a mode zero color error value. According to mode one, representative color values for each of at least three luminance levels are also generated to produce at least three representative color values, corresponding bitmap values and a mode one color error value. A mode based compressed data generator is capable of operating in mode zero and/or one and produces block color mode zero data when the mode zero color error value is less than the mode one color error value, otherwise block color mode one data.

10. 发明授权

US06937246B2 Cache invalidation method and apparatus for a graphics processing system 有权
标题翻译：用于图形处理系统的缓存无效方法和装置
公开(公告)号：US06937246B2
公开(公告)日：2005-08-30
申请号：US10775299
申请日：2004-02-09
申请人： Aaftab Munshi , James R. Peterson
发明人： Aaftab Munshi , James R. Peterson
IPC分类号： G06F12/08 , G09G5/36
CPC分类号： G06F12/0891 , G06F12/0875
摘要： A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.
摘要翻译：用于图形系统的缓存，其存储存储在数据高速缓存中的每个数据块的地址标签和标识号。将所请求的数据块的地址和标识号提供给高速缓存，并且针对存在的所有地址和标识号条目进行检查。如果请求的数据的地址和标识号都与缓存中的条目匹配，则提供数据块。然而，如果请求的数据的地址不存在，或者如果地址与条目匹配，但相关的标识号不匹配，则发生高速缓存未命中，并且必须从系统存储器检索所请求的图形数据。更新地址和标识号，并且所请求的数据替换数据高速缓存中的原来的图形数据。结果，存储在具有与所请求的数据相同的地址但具有无效的数据的高速缓存中的数据块可以无效而不使整个高速缓存无效。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式