专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09251116B2 Direct interthread communication dataport pack/unpack and load/save 有权
标题翻译：直接interthread通信数据端口包/解包和加载/保存
公开(公告)号：US09251116B2
公开(公告)日：2016-02-02
申请号：US13307609
申请日：2011-11-30
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/78
CPC分类号： G06F15/7832 , G06F15/7825
摘要： A circuit arrangement, method, and program product for compressing and decompressing data in a node of a system including a plurality of nodes interconnected via an on-chip network. Compressed data may be received and stored at an input buffer of a node, and in parallel with moving the compressed data to an execution register of the node, decompression logic of the node may decompress the data to generate uncompressed data, such that uncompressed data is stored in the execution register for utilization by an execution unit of the node. Uncompressed data may be output by the execution unit into the execution register, and in parallel with moving the uncompressed data to an output buffer of the node connected to the on-chip network, compression logic may compress the uncompressed data to generate compressed data, such that compressed data is stored at the output buffer.
摘要翻译：一种用于在包括通过片上网络互连的多个节点的系统的节点中压缩和解压缩数据的电路装置，方法和程序产品。压缩数据可以被接收并存储在节点的输入缓冲器处，并且与将压缩数据移动到节点的执行寄存器并行地，节点的解压缩逻辑可以解压缩数据以生成未压缩数据，使得未压缩数据为存储在执行寄存器中以供节点的执行单元利用。未经压缩的数据可以由执行单元输出到执行寄存器中，并且与将未压缩数据移动到连接到片上网络的节点的输出缓冲器并行地，压缩逻辑可压缩未压缩数据以产生压缩数据，该压缩数据被存储在输出缓冲器中。

2. 发明授权

US08935694B2 System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions 有权
标题翻译：用于通过单独的管理程序模式和访客模式和/或用户模式指令选择性地保存和恢复分支预测逻辑的状态的系统和方法
公开(公告)号：US08935694B2
公开(公告)日：2015-01-13
申请号：US13355884
申请日：2012-01-23
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/455 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30 , G06F9/3844 , G06F9/3848 , G06F9/3863
摘要： A hypervisor and one or more programs, e.g., guest operating systems and/or user processes or applications hosted by the hypervisor to configured to selectively save and restore the state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic.
摘要翻译：虚拟机管理程序和一个或多个程序，例如由虚拟机管理程序托管的客户操作系统和/或用户进程或应用程序，用于通过单独的管理程序模式和访客模式和/或用户选择性地保存和恢复分支预测逻辑的状态模式说明。通过这样做，不同的分支预测策略可以用于托管的不同操作系统和用户应用，从而提供分支预测逻辑的更细粒度优化。

3. 发明授权

US08880852B2 Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address 有权
标题翻译：基于操作码和操作数检测逻辑上的非有效操作，并设置标志将后续指令中指定的地址解码为不同的地址
公开(公告)号：US08880852B2
公开(公告)日：2014-11-04
申请号：US13281958
申请日：2011-10-26
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/318 , G06F9/00 , G06F9/30 , G06F9/34
CPC分类号： G06F9/00 , G06F9/30145 , G06F9/3016 , G06F9/30178 , G06F9/30181 , G06F9/34
摘要： A method, apparatus, and program product execute instructions of an instruction stream and detect logically non-significant operations in the instruction stream. Then, based on that detection, a target or source address of a subsequent instruction is adjusted. In some instances, doing so enables a greater number of addresses, e.g., registers, to be accessed in a given number of bit positions within an instruction format.
摘要翻译：方法，装置和程序产品执行指令流的指令并且检测指令流中的逻辑上非有效操作。然后，基于该检测，调整后续指示的目标或源地址。在一些情况下，这样做使得能够在指令格式中的给定数量的位位置中访问更多数量的地址，例如寄存器。

4. 发明授权

US08751830B2 Memory address translation-based data encryption/compression 失效
标题翻译：基于内存地址转换的数据加密/压缩
公开(公告)号：US08751830B2
公开(公告)日：2014-06-10
申请号：US13355806
申请日：2012-01-23
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F12/10 , G06F21/02
CPC分类号： G06F21/6218 , G06F12/10 , G06F12/1408 , G06F12/145
摘要： A method and circuit arrangement selectively stream data to an encryption or compression engine based upon encryption and/or compression-related page attributes stored in a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB). A memory address translation data structure may be accessed, for example, in connection with a memory access request for data in a memory page, such that attributes associated with the memory page in the data structure may be used to control whether data is encrypted/decrypted and/or compressed/decompressed in association with handling the memory access request.
摘要翻译：基于存储在存储器地址转换数据结构（例如有效到真实翻译（ERAT）或翻译后备缓冲器（TLB））中的加密和/或压缩相关页面属性，方法和电路装置有选择地将数据流传输到加密或压缩引擎，。存储器地址转换数据结构可以例如结合存储器页面中的数据的存储器访问请求来访问，使得与数据结构中的存储器页面相关联的属性可以用于控制数据是否被加密/解密和/或与处理存储器访问请求相关联地进行压缩/解压缩。

5. 发明授权

US08522254B2 Programmable integrated processor blocks 失效
标题翻译：可编程集成处理器模块
公开(公告)号：US08522254B2
公开(公告)日：2013-08-27
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F3/00 , G06F15/00
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译：芯片上的网络的集成处理器块可编程以执行第一功能。集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问到片上存储器。

6. 发明申请

US20130191651A1 MEMORY ADDRESS TRANSLATION-BASED DATA ENCRYPTION WITH INTEGRATED ENCRYPTION ENGINE 有权
标题翻译：基于内存地址转换的数据加密与集成加密引擎
公开(公告)号：US20130191651A1
公开(公告)日：2013-07-25
申请号：US13355827
申请日：2012-01-23
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F12/0848 , G06F12/1027 , G06F12/145 , G06F21/72 , G06F2212/1016 , G06F2212/1052 , G06F2212/402
摘要： A method and circuit arrangement utilize an integrated encryption engine within a processing core of a multi-core processor to perform encryption operations, i.e., encryption and decryption of secure data, in connection with memory access requests that access such data. The integrated encryption engine is utilized in combination with a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB) that is augmented with encryption-related page attributes to indicate whether pages of memory identified in the data structure are encrypted such that secure data associated with a memory access request in the processing core may be selectively streamed to the integrated encryption engine based upon the encryption-related page attribute for the memory page associated with the memory access request.
摘要翻译：一种方法和电路装置利用多核处理器的处理核心内的集成加密引擎，结合访问这些数据的存储器访问请求执行加密操作，即安全数据的加密和解密。集成加密引擎与诸如有效到实际翻译（ERAT）或翻译后备缓冲器（TLB）的存储器地址转换数据结构结合使用，其被加密与加密相关的页面属性，以指示是否在数据结构被加密，使得与处理核心中的存储器访问请求相关联的安全数据可以基于与存储器访问请求相关联的存储器页面的与加密相关的页面属性来选择性地流式传输到集成加密引擎。

7. 发明申请

US20130159676A1 INSTRUCTION SET ARCHITECTURE WITH EXTENDED REGISTER ADDRESSING 有权
标题翻译：具有扩展寄存器寻址的指令集架构
公开(公告)号：US20130159676A1
公开(公告)日：2013-06-20
申请号：US13330804
申请日：2011-12-20
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/30101 , G06F9/30138 , G06F9/30189 , G06F9/342
摘要： A method and circuit arrangement selectively repurpose bits from a primary opcode portion of an instruction for use in decoding one or more operands for the instruction. Decode logic of a processor, for example, may be placed in a predetermined mode that decodes a primary opcode for an instruction that is different from that specified in the primary opcode portion of the instruction, and then utilize one or more bits in the primary opcode portion to decode one or more operands for the instruction. By doing so, additional space is freed up in the instruction to support a larger register file and/or additional instruction types, e.g., as specified by a secondary or extended opcode.
摘要翻译：一种方法和电路装置选择性地对来自用于解码指令的一个或多个操作数的指令的主操作码部分的位进行重新排序。例如，处理器的解码逻辑可以被放置在对于与指令的主操作码部分中指定的指令不同的指令的主操作码进行解码的预定模式中，然后利用主操作码中的一个或多个位部分来解码指令的一个或多个操作数。通过这样做，在指令中释放额外的空间以支持更大的寄存器文件和/或附加指令类型，例如由辅助或扩展操作码指定。

8. 发明申请

US20130159675A1 INSTRUCTION PREDICATION USING UNUSED DATAPATH FACILITIES 有权
标题翻译：使用未使用的DATAPATH设备的指导性预测
公开(公告)号：US20130159675A1
公开(公告)日：2013-06-20
申请号：US13330102
申请日：2011-12-19
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/38 , G06F9/34 , G06F9/312
CPC分类号： G06F9/30181 , G06F9/30072 , G06F9/30101 , G06F9/30185 , G06F9/3802
摘要： A method and circuit arrangement for selectively predicating an instruction in an instruction stream based upon a value corresponding to a predication register address indicated by a portion of an operand associated with the instruction. A first compare instruction in an instruction stream stores a compare result in at a register address of a predication register. The register address of the predication register is stored in a portion of an operand associated with a second instruction, and during decoding the second instruction, the predication register is accessed to determine a value stored at the register address of the predication register, and the second instruction is selectively predicated based on the value stored at the register address of the predication register.
摘要翻译：一种方法和电路装置，用于基于与由指令相关联的操作数的一部分所指示的预测寄存器地址对应的值选择性地预测指令流中的指令。指令流中的第一比较指令将比较结果存储在预测寄存器的寄存器地址中。预测寄存器的寄存器地址存储在与第二指令相关联的操作数的一部分中，并且在解码第二指令期间，访问预测寄存器以确定存储在预测寄存器的寄存器地址处的值，而第二指令基于存储在预测寄存器的寄存器地址的值来选择性地预测指令。

9. 发明申请

US20120084535A1 Opcode Space Minimizing Architecture Utilizing Instruction Address to Indicate Upper Address Bits 有权
标题翻译：操作码空间最小化使用指令地址来指示上位地址的架构
公开(公告)号：US20120084535A1
公开(公告)日：2012-04-05
申请号：US12894697
申请日：2010-09-30
申请人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/3016 , G06F9/30181 , G06F9/345 , G06F9/3824
摘要： Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the upper address bits of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory.
摘要翻译：由于现代微处理器内核中的寄存器数量和新指令的数量不断增加，指令编码中存在的地址宽度不断扩大，更少的指令操作码可用，使得更难于将现有架构的新指令添加到现有的架构中，而无需使用不正当的具有诸如源破坏性操作等缺点的技巧。所公开的发明利用专门的解码和地址计算硬件，其将指令地址的固定数目的最低有效位连接到包含在指令中的每个寄存器地址部分的高地址位，从而产生完整寄存器地址，而不是提供完整寄存器指令中使用的每个寄存器的地址宽度。这释放了其他指令的有价值的操作码空间，避免了编译器的复杂性。这很好地与汇编语言中大多数循环展开的方式保持一致，独立操作在内存中彼此靠近。

10. 发明申请

US20110321049A1 Programmable Integrated Processor Blocks 失效
标题翻译：可编程集成处理器模块
公开(公告)号：US20110321049A1
公开(公告)日：2011-12-29
申请号：US12823745
申请日：2010-06-25
申请人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
发明人： Mark J. Hickey , Eric O. Mejdrich , Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F9/46 , G06F9/318
CPC分类号： G06F15/7825 , G06F9/3879
摘要： An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory.
摘要翻译：芯片上的网络的集成处理器块可编程以执行第一功能。集成处理器块包括用于从芯片上的网络的其他集成处理器块接收传入分组的收件箱，向其他集成处理器块发送输出分组的发送箱，片上存储器和存储器管理单元，以使得能够访问到片上存储器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式