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1. 发明授权

US09632779B2 Instruction predication using instruction filtering 有权
公开(公告)号：US09632779B2
公开(公告)日：2017-04-25
申请号：US13329575
申请日：2011-12-19
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F9/30101 , G06F9/30185
摘要： A method and circuit arrangement for selectively predicating instructions in an instruction stream based upon a predication filter criteria defined by a predication filter, which describes types or patterns of instructions that should be predicated. Predication logic compares a respective instruction of an instruction stream to predication filter criteria to determine whether the respective instruction matches the predication filter criteria, and the respective instruction is selectively predicated based on whether the respective instruction matches the predication filter criteria.

2. 发明授权

US09354887B2 Instruction buffer bypass of target instruction in response to partial flush 有权
标题翻译：指令缓冲区绕目标指令响应部分刷新
公开(公告)号：US09354887B2
公开(公告)日：2016-05-31
申请号：US12824812
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3814 , G06F9/3861 , G06F12/0853 , G06F2205/065
摘要： A circuit arrangement and method selectively bypass an instruction buffer for selected instructions so that bypassed instructions can be dispatched without having to first pass through the instruction buffer. Thus, for example, in the case that an instruction buffer is partially or completely flushed as a result of an instruction redirect (e.g., due to a branch mispredict), instructions can be forwarded to subsequent stages in an instruction unit and/or to one or more execution units without the latency associated with passing through the instruction buffer.
摘要翻译：电路装置和方法选择性地旁路用于所选指令的指令缓冲器，使得可以调度旁路指令而不必首先通过指令缓冲器。因此，例如，在指令重定向（例如，由于分支错误预测）导致指令缓冲器被部分或全部冲洗的情况下，可以将指令转发到指令单元中的后续阶段和/或向一个或更多的执行单元，而没有与通过指令缓冲器相关联的延迟。

3. 发明授权

US09176885B2 Combined cache inject and lock operation 有权
标题翻译：组合缓存注入和锁定操作
公开(公告)号：US09176885B2
公开(公告)日：2015-11-03
申请号：US13355613
申请日：2012-01-23
申请人： Jamie R. Kuesel , Mark G. Kupferschmidt , Paul E. Schardt , Robert A. Shearer, III
发明人： Jamie R. Kuesel , Mark G. Kupferschmidt , Paul E. Schardt , Robert A. Shearer, III
IPC分类号： G06F13/00 , G06F12/08 , G06F13/28
CPC分类号： G06F12/0888 , G06F13/28
摘要： A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.
摘要翻译：电路装置和方法利用高速缓存注入逻辑来执行高速缓存注入和锁定操作，以将高速缓存行注入到高速缓冲存储器中，并且将高速缓存行与高速缓存行的通信并行地主动地锁定在高速缓存存储器中。高速缓存注入逻辑可以另外限制可以存储在高速缓冲存储器中的锁定高速缓存行的最大数量，例如通过中止高速缓存注入和锁定操作，在不锁定的情况下注入高速缓存行，或者解锁和/或驱逐另一个高速缓存行在缓存中。

4. 发明授权

US09075623B2 External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit 有权
标题翻译：外部辅助执行单元接口，用于从发布单元到片外辅助执行单元的指令格式转换
公开(公告)号：US09075623B2
公开(公告)日：2015-07-07
申请号：US13352907
申请日：2012-01-18
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Corey V. Swenson
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Corey V. Swenson
IPC分类号： G06F9/38 , G06F15/80 , G06F15/78
CPC分类号： G06F9/3881 , G06F9/3877 , G06F15/7864 , G06F15/8038
摘要： An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.
摘要翻译：在设置在第一可编程芯片中的处理核心和设置在第二可编程芯片中的芯片外AXU之间提供外部辅助执行单元（AXU）接口，以将AXU与发行单元，固定点执行单元以及可选地处理核心中的其他功能单元。外部AXU接口使发布单元能够以与发布单元能够向安置在同一芯片上的AXU发出指令的方式大致相同的方式向AXU发出指令。通过这样做，可以独立于第一可编程芯片上的处理核心设计，测试和验证第二可编程芯片上的AXU，从而使已经设计，测试和验证的公共处理核心被用于连接多个不同的AXU设计。

5. 发明授权

US09032191B2 Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels 有权
标题翻译：分支预测逻辑的虚拟化支持在管理程序和客户机操作系统级别启用/禁用
公开(公告)号：US09032191B2
公开(公告)日：2015-05-12
申请号：US13355863
申请日：2012-01-23
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/38
CPC分类号： G06F9/3848 , G06F9/3842 , G06F9/3844 , G06F9/45558
摘要： A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.
摘要翻译：驻留在数据处理系统中并由管理程序托管的管理程序和一个或多个客户操作系统被配置为通过单独的管理程序模式和访客模式指令选择性地启用或禁用分支预测逻辑。通过这样做，不同的分支预测策略可以用于托管的不同操作系统和用户应用，从而为不同的操作场景提供分支预测逻辑的更细粒度优化。

6. 发明授权

US08949836B2 Transferring architected state between cores 有权
公开(公告)号：US08949836B2
公开(公告)日：2015-02-03
申请号：US13078263
申请日：2011-04-01
申请人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Robert A. Shearer , Alfred T. Watson, III
IPC分类号： G06F9/46 , G06F9/30 , G06F9/48
CPC分类号： G06F9/30043 , G06F9/3009 , G06F9/46 , G06F9/4856
摘要： A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.

7. 发明授权

US08892851B2 Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions 有权
标题翻译：当相同的目的地址不通过介入指令用作源地址时，更改随后指令的操作码
公开(公告)号：US08892851B2
公开(公告)日：2014-11-18
申请号：US13287412
申请日：2011-11-02
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/318 , G06F9/30
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30181 , G06F9/3832
摘要： A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second opcode in response to detecting successive address targeting. The circuit arrangement and method execute instructions in an instruction stream and detect successive address targeting by two or more instructions in the instruction stream without the targeted address being utilized as a source address in an instruction executed between the first and second instructions in the instruction stream. Then, based on that detection, the opcode of the second instruction is modified, changed, or appended to such that a different opcode is indicated by the second instruction, such that executing the second instruction causes a different unique type of operation to be performed.
摘要翻译：电路布置和方法通过响应于检测到连续的地址目标来检测连续的地址目标和将指令的第一操作码解码成第二操作码来支持指令操作码的压缩和扩展。电路装置和方法在指令流中执行指令，并且在指令流中的指令流中的第一和第二指令之间执行的指令中，用目标地址作为源地址来检测指令流中两个或多个指令的连续地址定向。然后，基于该检测，第二指令的操作码被修改，改变或附加，使得由第二指令指示不同的操作码，使得执行第二指令导致执行不同的独特类型的操作。

8. 发明授权

US08549262B2 Instruction operand addressing using register address sequence detection 失效
标题翻译：指令操作数寻址使用寄存器地址序列检测
公开(公告)号：US08549262B2
公开(公告)日：2013-10-01
申请号：US12778635
申请日：2010-05-12
申请人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/30065 , G06F9/30098 , G06F9/30101 , G06F9/3016
摘要： A circuit arrangement and method support efficient indexing into large register files by utilizing register address sequence detection, wherein register addresses to be used by an instruction are produced by concatenating a portion of the address that is contained in the instruction with another portion that is speculatively produced by sequence detection logic. The portion of the correct full address that is not contained in the instruction is stored in a software accessible special purpose register. If the end of a particular sequence of addresses is detected by the sequence detection logic, the invention speculatively assumes that the next address in the sequence will be used. Since only a portion of the full addresses are stored in the instruction, they occupy less instruction space than the full address widths. An instruction may include at least one address portion that identifies a register address.
摘要翻译：电路布置和方法通过利用寄存器地址序列检测来支持对大型寄存器文件的高效索引，其中由指令使用的寄存器地址是通过将指令中包含的地址的一部分连接到被推测产生的另一部分来产生的通过序列检测逻辑。指令中未包含的正确完整地址的部分存储在软件可访问的专用寄存器中。如果由序列检测逻辑检测到特定地址序列的结尾，则本发明推测地假定序列中的下一个地址将被使用。由于只有一部分完整地址存储在指令中，所以占用的地址宽度比完整地址少。指令可以包括标识寄存器地址的至少一个地址部分。

9. 发明申请

US20130191824A1 VIRTUALIZATION SUPPORT FOR BRANCH PREDICTION LOGIC ENABLE/DISABLE 有权
标题翻译：支持分支预测逻辑的虚拟化支持启用/禁用
公开(公告)号：US20130191824A1
公开(公告)日：2013-07-25
申请号：US13355863
申请日：2012-01-23
申请人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/455
CPC分类号： G06F9/3848 , G06F9/3842 , G06F9/3844 , G06F9/45558
摘要： A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.
摘要翻译：驻留在数据处理系统中并由管理程序托管的管理程序和一个或多个客户操作系统被配置为通过单独的管理程序模式和访客模式指令选择性地启用或禁用分支预测逻辑。通过这样做，不同的分支预测策略可以用于托管的不同操作系统和用户应用，从而为不同的操作场景提供分支预测逻辑的更细粒度优化。

10. 发明申请

US20130185542A1 EXTERNAL AUXILIARY EXECUTION UNIT INTERFACE TO OFF-CHIP AUXILIARY EXECUTION UNIT 有权
标题翻译：外部辅助执行单元接口切换辅助执行单元
公开(公告)号：US20130185542A1
公开(公告)日：2013-07-18
申请号：US13352907
申请日：2012-01-18
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Corey V. Swenson
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Corey V. Swenson
IPC分类号： G06F9/30
CPC分类号： G06F9/3881 , G06F9/3877 , G06F15/7864 , G06F15/8038
摘要： An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.
摘要翻译：在设置在第一可编程芯片中的处理核心和设置在第二可编程芯片中的芯片外AXU之间提供外部辅助执行单元（AXU）接口，以将AXU与发行单元，固定点执行单元以及可选地处理核心中的其他功能单元。外部AXU接口使发布单元能够以与发布单元能够向安置在同一芯片上的AXU发出指令的方式大致相同的方式向AXU发出指令。通过这样做，可以独立于第一可编程芯片上的处理核心设计，测试和验证第二可编程芯片上的AXU，从而使已经设计，测试和验证的公共处理核心被用于连接多个不同的AXU设计。

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