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1. 发明授权

US07724093B2 Phase locked loop with two-step control 有权
标题翻译：具有两步控制的锁相环
公开(公告)号：US07724093B2
公开(公告)日：2010-05-25
申请号：US12139291
申请日：2008-06-13
申请人： Alexander Wormer , Harald Sandner
发明人： Alexander Wormer , Harald Sandner
IPC分类号： H03L7/085 , H03L7/089 , H03L7/099
CPC分类号： H03L7/113 , H03L7/087 , H03L7/089 , H03L7/093 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (fOSC), a clock divider coupled to the DCO and receiving the DCO output signal and outputting a feedback clock signal (fN), and a phase frequency detector (PFD) coupled to the DCO and controlling the DCO by a DCO control signal (dCNTL). The PFD has a first input for receiving the feedback clock signal (fN), a second input for receiving a reference clock signal (fREF), and comprises a frequency detection stage (FD) adapted to calculate a frequency difference between the feedback clock signal (fN) and the reference clock signal (fREF) in a frequency detection mode and to adjust the DCO control signal based on said frequency difference, a phase detection (PD) stage for calculating a phase error between the feedback clock signal and the reference clock signal in a phase detection mode, and a switch for switching between the frequency detection mode and the phase detection mode upon the frequency of the feedback clock signal reaching a predetermined value.
摘要翻译：锁相环具有用于产生DCO输出信号（fOSC）的数字控制振荡器（DCO），耦合到DCO并接收DCO输出信号并输出反馈时钟信号（fN）的时钟分频器，以及相位频率检测器（PFD）耦合到DCO并通过DCO控制信号（dCNTL）控制DCO。 PFD具有用于接收反馈时钟信号（fN）的第一输入端，用于接收基准时钟信号（fREF）的第二输入端，并且包括频率检测级（FD），该频率检测级适于计算反馈时钟信号 fN）和参考时钟信号（fREF），并且基于所述频率差调整DCO控制信号;相位检测（PD）级，用于计算反馈时钟信号和参考时钟信号之间的相位误差在相位检测模式中，以及用于在反馈时钟信号的频率达到预定值时在频率检测模式和相位检测模式之间切换的开关。

2. 发明申请

US20080309421A1 PHASE LOCKED LOOP WITH TWO-STEP CONTROL 有权
标题翻译：两相控制的锁相环
公开(公告)号：US20080309421A1
公开(公告)日：2008-12-18
申请号：US12139291
申请日：2008-06-13
申请人： Alexander Wormer , Harald Sandner
发明人： Alexander Wormer , Harald Sandner
IPC分类号： H03L7/085
CPC分类号： H03L7/113 , H03L7/087 , H03L7/089 , H03L7/093 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A phase locked loop has a digitally controlled oscillator (DCO) for generating a DCO output signal (fOSC), a clock divider coupled to the DCO and receiving the DCO output signal and outputting a feedback clock signal (fN), and a phase frequency detector (PFD) coupled to the DCO and controlling the DCO by a DCO control signal (dCNTL). The PFD has a first input for receiving the feedback clock signal (fN), a second input for receiving a reference clock signal (fREF), and comprises a frequency detection stage (FD) adapted to calculate a frequency difference between the feedback clock signal (fN) and the reference clock signal (fREF) in a frequency detection mode and to adjust the DCO control signal based on said frequency difference, a phase detection (PD) stage for calculating a phase error between the feedback clock signal and the reference clock signal in a phase detection mode, and a switch for switching between the frequency detection mode and the phase detection mode upon the frequency of the feedback clock signal reaching a predetermined value.
摘要翻译：锁相环具有用于产生DCO输出信号（fOSC）的数字控制振荡器（DCO），耦合到DCO并接收DCO输出信号并输出反馈时钟信号（fN）的时钟分频器，以及相位频率检测器（PFD）耦合到DCO并通过DCO控制信号（dCNTL）控制DCO。 PFD具有用于接收反馈时钟信号（fN）的第一输入端，用于接收基准时钟信号（fREF）的第二输入端，并且包括频率检测级（FD），该频率检测级适于计算反馈时钟信号 fN）和参考时钟信号（fREF），并且基于所述频率差调整DCO控制信号;相位检测（PD）级，用于计算反馈时钟信号和参考时钟信号之间的相位误差在相位检测模式中，以及用于在反馈时钟信号的频率达到预定值时在频率检测模式和相位检测模式之间切换的开关。

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