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    • 1. 发明授权
    • Heterodyne receiver
    • 外差接收机
    • US07962112B2
    • 2011-06-14
    • US11954136
    • 2007-12-11
    • Harald SandnerAjaib Hussain
    • Harald SandnerAjaib Hussain
    • H04B1/06H04K3/00
    • H03G3/3078H03G3/3068
    • A heterodyne receiver comprising a gain controllable RF mixer (14) which has a first input connected to a first local oscillator (16) and a second input connected to an RF input. The receiver comprises a peak detector (38) which detects a peak value of an input signal at the second input of the HF mixer and generates a digital control signal if it is determined that the peak value of the input signal is above a predetermined level. A digital automatic gain control circuit (34) decreases upon reception of the digital control signal the gain of the RF mixer.
    • 一种外差接收器,包括增益可控RF混频器(14),其具有连接到第一本地振荡器(16)的第一输入端和连接到RF输入端的第二输入端。 接收机包括峰值检测器(38),其在HF混频器的第二输入端检测输入信号的峰值,并且如果确定输入信号的峰值高于预定电平则产生数字控制信号。 数字自动增益控制电路(34)在接收到数字控制信号时降低RF混频器的增益。
    • 2. 发明申请
    • HETERODYNE RECEIVER
    • 异位接收器
    • US20080153445A1
    • 2008-06-26
    • US11954136
    • 2007-12-11
    • Harald SandnerAjaib Hussain
    • Harald SandnerAjaib Hussain
    • H04B1/06
    • H03G3/3078H03G3/3068
    • A heterodyne receiver comprising a gain controllable RF mixer (14) which has a first input connected to a first local oscillator (16) and a second input connected to an RF input. The receiver comprises a peak detector (38) which detects a peak value of an input signal at the second input of the HF mixer and generates a digital control signal if it is determined that the peak value of the input signal is above a predetermined level. A digital automatic gain control circuit (34) decreases upon reception of the digital control signal the gain of the RF mixer.
    • 一种外差接收器,包括增益可控RF混频器(14),其具有连接到第一本地振荡器(16)的第一输入端和连接到RF输入端的第二输入端。 接收机包括峰值检测器(38),其在HF混频器的第二输入端检测输入信号的峰值,并且如果确定输入信号的峰值高于预定电平则产生数字控制信号。 数字自动增益控制电路(34)在接收到数字控制信号时降低RF混频器的增益。
    • 3. 发明申请
    • ALL DIGITAL PHASE LOCKED LOOP SYSTEM AND METHOD
    • 所有数字相位锁定系统和方法
    • US20070200638A1
    • 2007-08-30
    • US11624149
    • 2007-01-17
    • HARALD SANDNERHARALD PARZHUBER
    • HARALD SANDNERHARALD PARZHUBER
    • H03L7/00
    • H03L7/08H03L2207/50
    • An all digital PLL system generates an analog oscillator signal at intermediate frequencies to achieve averaged oscillator frequencies at an extremely high frequency resolution. The PLL system includes a digitally controlled oscillator (10) with a digital control input and an analog signal output, and a feedback loop with a digital loop filter (16) for generating a digital control signal for the digitally controlled oscillator (10). The digital loop filter (16) has a first output providing an integer part (nint) of the digital control signal and a second output providing a fractional part (nΣΔ) of the digital control signal. A sigma-delta modulator (14) has an input connected to the second output of the digital loop filter (16) and an output providing a one-bit digital output signal (ΣΔ), and a digital adder (12) has a first input connected to the first output of the digital loop filter (16), a second input connected to the output of the sigma-delta modulator (14), and an output connected to the digital control input of the digitally controlled oscillator (10). The output of the sigma-delta modulator (14) modulates the least significant bits from the first output of the digital loop filter (16).
    • 全数字PLL系统在中频产生模拟振荡器信号,以极高频率分辨率实现平均振荡器频率。 PLL系统包括具有数字控制输入和模拟信号输出的数字控制振荡器(10)和具有数字环路滤波器(16)的反馈回路,用于产生数字控制振荡器(10)的数字控制信号。 数字环路滤波器(16)具有第一输出,提供数字控制信号的整数部分(n int),第二输出提供小数部分(nSigmaDelta) 的数字控制信号。 Σ-Δ调制器(14)具有连接到数字环路滤波器(16)的第二输出的输入端和提供一比特数字输出信号(SigmaDelta)的输出,数字加法器(12)具有第一输入 连接到数字环路滤波器(16)的第一输出,连接到Σ-Δ调制器(14)的输出端的第二输入端和连接到数字控制振荡器(10)的数字控制输入端的输出端。 Σ-Δ调制器(14)的输出调制来自数字环路滤波器(16)的第一输出的最低有效位。
    • 8. 发明申请
    • Highspeed serial transmission system and a method for reducing jitter in data transfer on such a system
    • 高速串行传输系统和减少这种系统上的数据传输抖动的方法
    • US20070063880A1
    • 2007-03-22
    • US11384600
    • 2006-03-20
    • Joerg GollerHarald Sandner
    • Joerg GollerHarald Sandner
    • H03M9/00
    • H03K5/1565H04L1/205H04L7/0025H04L25/03343
    • In a high-speed serial transmission system (10) comprising a transmitter (12), a transmission line (14) and a receiver (16), the transmitter (12) includes a bit-stream generator (18) for generating a predetermined pseudo random bit sequence (PRBS), and a controllable phase distortion circuit (20) having an input (24) connected to the bit-stream generator (18) and a signal output (26) connected to the transmission line (14). The receiver (16) includes a sampling circuit (30) with a signal input (36) connected to the transmission line (14), a sampling clock input (38) and a data output (40), a clock recovery circuit (32) with a phase-locked loop circuit (42) and a controllable phase interpolator (44) that has signal inputs (45) connected to signal outputs of the phase-locked loop circuit (42) and an output (48) connected to the sampling clock input (38) of the sampling circuit (30), and a bit-stream verification circuit (32) with an input (50) connected to the data output (40) of the sampling circuit (30) and an output (52) that controls the controllable phase interpolator. An output (54) of the bit-stream verification circuit (34) controls the controllable phase distortion circuit (20) in the transmitter (12) in response to a bit error rate (BER) detected in the bit-stream received form the data output (40) of the sampling circuit (30) by comparison with the predetermined pseudo random bit sequence (PRBS).
    • 在包括发射机(12),传输线(14)和接收机(16)的高速串行传输系统(10)中,发射器(12)包括位流发生器(18),用于产生预定的伪 随机比特序列(PRBS)和具有连接到比特流发生器(18)的输入(24)和连接到传输线(14)的信号输出(26)的可控相位失真电路(20)。 接收器(16)包括具有连接到传输线(14)的信号输入(36),采样时钟输入(38)和数据输出(40),时钟恢复电路(32)的采样电路(30) 具有锁相环电路(42)和可控相位内插器(44),其具有连接到锁相环电路(42)的信号输出的信号输入(45)和连接到采样时钟的输出(48) 采样电路(30)的输入(38)和连接到采样电路(30)的数据输出(40)的输入(50)的位流验证电路(32)和输出(52), 控制可控相位内插器。 比特流验证电路(34)的输出(54)响应于从数据接收的比特流中检测到的比特误码率(BER)来控制发射机(12)中的可控相位失真电路(20) 通过与预定伪随机比特序列(PRBS)进行比较,采样电路(30)的输出(40)。