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1. 发明授权

US07506287B2 Method, system, and program product for pre-compile processing of hardware design language (HDL) source files 失效
标题翻译：方法，系统和程序产品，用于硬件设计语言（HDL）源文件的预编译处理
公开(公告)号：US07506287B2
公开(公告)日：2009-03-17
申请号：US11521917
申请日：2006-09-16
申请人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket , Hussein Sharafeddin
发明人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket , Hussein Sharafeddin
IPC分类号： G06F17/50
CPC分类号： G06F11/3664 , G06F8/447
摘要： A method includes pre-compilation operations on HDL source code files, creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded function and operator calls in an HDL source code browser debugger. Construct a list of all HDL files a list of HDL files to be processed. Send an HDL file in the list for compiling. If compilation is successful, branch to add the HDL file to an end of target file and that HDL file is removed from the list. The list is tested for remaining files and then a next file in the list is sent for compiling. After all files in the list have been processed, the HDL files which have been processed are checked for failures to compile and if any of said HDL files to be processed have failed to compile the method branches back to repeating the process until all runs are successful.
摘要翻译：一种方法包括对HDL源代码文件进行预编译操作，在HDL源浏览器中创建“make it”文件，按需处理HDL源代码，并在HDL源代码浏览器调试器中解析重载函数和操作符调用。构建所有HDL文件的列表，列出要处理的HDL文件。在列表中发送一个HDL文件进行编译。如果编译成功，请将HDL文件添加到目标文件的末尾，并从列表中删除该HDL文件。该列表被测试剩余的文件，然后发送列表中的下一个文件进行编译。在处理列表中的所有文件之后，检查已处理的HDL文件，以便编译失败，并且如果要处理的所有HDL文件中的任何一个无法编译方法分支回到重复进程，直到所有运行成功。

2. 发明申请

US20080072206A1 Unrolling Hardware Design Generate Statements in a Source Window Debugger 有权
标题翻译：展开硬件设计在源窗口生成语句调试器
公开(公告)号：US20080072206A1
公开(公告)日：2008-03-20
申请号：US11532216
申请日：2006-09-15
申请人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket
发明人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.
摘要翻译：展开硬件描述语言（“HDL”）的“生成”语句并显示展开的HDL。对于条件生成条件进行评估。如果声明为真，则将显示附带的HDL代码。对于迭代生成，封闭的HDL将被显示为迭代方案边界所指定的次数。这允许例如生成语句内声明的信号的模拟值注释，生成语句内的语义导航，并允许用户可视化目标设计中包含的内容。

3. 发明申请

US20060190867A1 Method for reconfiguration of random biases in a synthesized design without recompilation 有权
标题翻译：在没有重新编译的情况下，在合成设计中重新配置随机偏差的方法
公开(公告)号：US20060190867A1
公开(公告)日：2006-08-24
申请号：US11050232
申请日：2005-02-03
申请人： Jason Baumgartner , Ali El-Zein , Daniel Heller , Wolfgang Roesner
发明人： Jason Baumgartner , Ali El-Zein , Daniel Heller , Wolfgang Roesner
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver specification is then parsed into a base constraint and bias file, wherein the base constraint and bias file is suitable for conversion into one of a set comprising a netlist representation and a random simulation representation. A verification framework is selected from among a set comprising a random verification framework using the random simulation representation and a synthesized verification framework using the netlist representation. In response to selecting the random verification framework using the random simulation representation, the random simulation representation is compiled into a parameter database. In response to selecting the synthesized verification framework using the netlist representation, the netlist representation is compiled into a synthesized model. A property of at least one of a set of the synthesized model and the parameter database is tested and verified.
摘要翻译：公开了一种用于执行测试和验证的方法，系统和计算机程序产品。该方法包括将偏置数据规范转换为驱动器规范。然后将驱动器规范解析为基本约束和偏置文件，其中基本约束和偏置文件适于转换成包括网表表示和随机模拟表示的集合之一。从包括使用随机模拟表示的随机验证框架的集合和使用网表表示的合成验证框架中选择验证框架。响应于使用随机模拟表示法选择随机验证框架，随机模拟表示被编译成参数数据库。响应于使用网表表示来选择合成的验证框架，网表表示被编译成合成模型。测试和验证合成模型和参数数据库中的至少一个的属性。

4. 发明申请

US20130198705A1 CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US20130198705A1
公开(公告)日：2013-08-01
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

5. 发明授权

US08230406B2 Compiler option consistency checking during incremental hardware design language compilation 失效
标题翻译：增量硬件设计语言编译期间的编译器选项一致性检查
公开(公告)号：US08230406B2
公开(公告)日：2012-07-24
申请号：US11530495
申请日：2006-09-11
申请人： Richard L. H. Carbone , Gabor Bobok , Gabor Drasny , Ali El-Zein
发明人： Richard L. H. Carbone , Gabor Bobok , Gabor Drasny , Ali El-Zein
IPC分类号： G06F9/45
CPC分类号： G06F17/505 , G06F8/48
摘要： Method, system, and program product for processing hardware design language code to facilitate reuse of compiled code units including options and option values in compiled code units. The method includes the steps of grouping options and option values to determine if code controlled by them will be reused; and determining options and option values that would permit and prevent reuse of compiled code units.
摘要翻译：用于处理硬件设计语言代码的方法，系统和程序产品，以便于编译代码单元的重用，包括编译代码单元中的选项和选项值。该方法包括对选项和选项值进行分组以确定由其控制的代码是否将被重用的步骤; 并确定允许和防止重用已编译代码单元的选项和选项值。

6. 发明申请

US20080127130A1 Compiler Option Consistency Checking During Incremental Hardware Design Language Compilation 失效
标题翻译：增量硬件设计语言编译期间的编译器选项一致性检查
公开(公告)号：US20080127130A1
公开(公告)日：2008-05-29
申请号：US11530495
申请日：2006-09-11
申请人： Richard L.H. Carbone , Gabor Bobok , Gabor Drasny , Ali El-Zein
发明人： Richard L.H. Carbone , Gabor Bobok , Gabor Drasny , Ali El-Zein
IPC分类号： G06F9/45
CPC分类号： G06F17/505 , G06F8/48
摘要： Method, system, and program product for processing hardware design language code to facilitate reuse of compiled code units including options and option values in compiled code units. The method includes the steps of grouping options and option values to determine if code controlled by them will be reused; and determining options and option values that would permit and prevent reuse of compiled code units.
摘要翻译：用于处理硬件设计语言代码的方法，系统和程序产品，以便于编译代码单元的重用，包括编译代码单元中的选项和选项值。该方法包括对选项和选项值进行分组以确定由其控制的代码是否将被重用的步骤; 并确定允许和防止重用已编译代码单元的选项和选项值。

7. 发明申请

US20080127126A1 Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing 失效
标题翻译：通过预处理将VHDL多等待行为FSM合成到RT级FSM中
公开(公告)号：US20080127126A1
公开(公告)日：2008-05-29
申请号：US11522036
申请日：2006-09-16
申请人： Gabor Drasny , Gabor Bobok , Ali El-Zein
发明人： Gabor Drasny , Gabor Bobok , Ali El-Zein
IPC分类号： G06F9/45
CPC分类号： G06F17/5054 , G06F17/5045
摘要： Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer
摘要翻译：预处理“等待”语句的并行序列，并合成这些多个“等待”语句来构建对RTL工具的支持。这是通过将具有多个等待语句（称为BehFSM）的VHDL进程预处理为等效的寄存器传输来实现的

8. 发明申请

US20080072187A1 Method, system, and program product for pre-compile processing of HDL source files 失效
标题翻译：用于HDL源文件预编译处理的方法，系统和程序产品
公开(公告)号：US20080072187A1
公开(公告)日：2008-03-20
申请号：US11521917
申请日：2006-09-16
申请人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket , Hussein Sharafeddin
发明人： Gabor Drasny , Gabor Bobok , Ali El-Zein , Fadi Zaraket , Hussein Sharafeddin
IPC分类号： G06F17/50
CPC分类号： G06F11/3664 , G06F8/447
摘要： Pre-compilation processing including pre-compilation operations on HDL source code files, including creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded function and operator calls in an HDL source code browser debugger
摘要翻译：预编译处理，包括HDL源代码文件的预编译操作，包括创建“制作”文件，在HDL源浏览器中对HDL源代码进行按需处理，以及解析HDL源代码中的过载功能和操作员调用浏览器调试器

9. 发明授权

US08495533B2 Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessing 失效
标题翻译：通过预处理将VHDL多等待行为FSM合成到RT级FSM中
公开(公告)号：US08495533B2
公开(公告)日：2013-07-23
申请号：US11522036
申请日：2006-09-16
申请人： Gabor Drasny , Gabor Bobok , Ali El-Zein
发明人： Gabor Drasny , Gabor Bobok , Ali El-Zein
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045
摘要： Preprocessing parallel sequences of “wait” statements and synthesizing these multiple “wait” statements to construct support for RTL tools. This is accomplished by preprocessing a VHDL process with multiple wait statements (referred to as BehFSM) into an equivalent register transfer.
摘要翻译：预处理“等待”语句的并行序列，并合成这些多个“等待”语句来构建对RTL工具的支持。这是通过将具有多个等待语句（称为BehFSM）的VHDL进程预处理为等效的寄存器传输来实现的。

10. 发明授权

US08640065B2 Circuit verification using computational algebraic geometry 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US08640065B2
公开(公告)日：2014-01-28
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

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