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1. 发明授权

US08171377B2 System to improve memory reliability and associated methods 有权
标题翻译：系统提高内存可靠性和相关方法
公开(公告)号：US08171377B2
公开(公告)日：2012-05-01
申请号：US12023374
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1044 , H03M13/1515
摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
摘要翻译：一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。

2. 发明授权

US07350126B2 Method for constructing erasure correcting codes whose implementation requires only exclusive ORs 有权
标题翻译：用于构造擦除纠正码的方法，其执行仅需要异或
公开(公告)号：US07350126B2
公开(公告)日：2008-03-25
申请号：US10600593
申请日：2003-06-23
申请人： Shmuel Winograd , Barry Marshall Trager
发明人： Shmuel Winograd , Barry Marshall Trager
IPC分类号： H03M13/00
CPC分类号： G06F11/1076 , H03M13/134 , H03M13/1515 , H03M13/373 , H03M13/616 , H03M13/6569
摘要： Error correcting codes of any distance (including codes of distance greater than four) use only exclusive OR (XOR) operations. Any code over a finite field of characteristic two are converted into a code whose encoding and correcting algorithms involve only XORs of words (and loading and storing of the data). Thus, the implementation of the encoding and correcting algorithms is more efficient, since it uses only XORs of words—an operation which is available on almost all microprocessors. An important code, the (3, 3) code of distance four, is also described.
摘要翻译：任何距离（包括距离大于4的码）的纠错码仅使用异或（XOR）操作。特征2的有限域上的任何代码被转换成代码，其编码和校正算法仅涉及字的异或（并且加载和存储数据）。因此，编码和校正算法的实现更有效，因为它仅使用字的异或 - 几乎所有微处理器都可用的操作。还描述了一个重要的代码，即距离四的（3，3）代码。

3. 发明申请

US20080016413A1 RAID 3 + 3 有权
公开(公告)号：US20080016413A1
公开(公告)日：2008-01-17
申请号：US11747887
申请日：2007-05-11
申请人： Steven Hetzler , Daniel Smith , Shmuel Winograd
发明人： Steven Hetzler , Daniel Smith , Shmuel Winograd
IPC分类号： G06F11/00
CPC分类号： G06F11/1076 , G06F2211/1057 , G06F2211/1059 , G06F2211/1064
摘要： A data storage subsystem that includes three data storage units, three check storage units, and an array controller coupled to the three data and three check storage units can tolerate failure of any three data and check storage units failures can be occur before data stored on the data storage subsystem is lost. Information is stored on the data storage subsystem as a symmetric Maximum Distance Separation code, such as a Winograd code, a Reed Solomon code, an EVENODD code or a derivative of an EVENODD code. The array controller determines the contents of the check storage units so that any three erasures of the data storage units and the check storage units can be corrected by the array controller. The array controller updates a block of data contained in any one of the data storage units and the check storage units using only six IO operations.
摘要翻译：包含三个数据存储单元，三个检查存储单元和耦合到三个数据的阵列控制器和三个检查存储单元的数据存储子系统可以容忍任何三个数据的故障，并且检查存储单元可能在存储在数据存储子系统丢失。信息作为对称的最大距离分离码存储在数据存储子系统上，例如Winograd码，里德所罗门码，EVENODD码或EVENODD码的导数。阵列控制器确定检查存储单元的内容，使得数据存储单元和检查存储单元的任何三个擦除可以由阵列控制器校正。阵列控制器仅使用六个IO操作来更新包含在数据存储单元和检查存储单元中的任何一个中的数据块。

4. 发明授权

US06792569B2 Root solver and associated method for solving finite field polynomial equations 失效
标题翻译：求解有限域多项式方程的根解和相关方法
公开(公告)号：US06792569B2
公开(公告)日：2004-09-14
申请号：US09842244
申请日：2001-04-24
申请人： Charles Edwin Cox , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
发明人： Charles Edwin Cox , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
IPC分类号： H03M1300
CPC分类号： H03M13/1545 , H03M13/1515
摘要： An error correction algebraic decoder uses a key equation solver for calculating the roots of finite field polynomial equations of degree up to six, and lends itself to efficient hardware implementation and low latency direction calculation. The decoder generally uses a two-step process. The first step is the conversion of quintic equations into sextic equations, and the second step is the adoption of an invertible Tschirnhausen transformation to reduce the sextic equations by eliminating the degree 5 term. The application of the Tschirnhausen transformation considerably decreases the complexity of the operations required in the transformation of the polynomial equation into a matrix. The second step defines a specific Gaussian elimination that separates the problem of solving quintic and sextic polynomial equations into a simpler problem of finding roots of a quadratic equation and a quartic equation.
摘要翻译：纠错代数解码器使用密钥方程求解器来计算六个有限域多项式方程的根，并适用于有效的硬件实现和低延迟方向计算。解码器通常采用两步法。第一步是将五次方程转换为性别方程，第二步是采用可逆的Tschirnhausen变换，通过消除5度项来减少性别方程。 Tschirnhausen变换的应用大大降低了将多项式方程转换为矩阵所需的操作的复杂性。第二步定义了一个特定的高斯消除，将解决五元和多项式多项式方程的问题分解成找到二次方程和四次方程的根的一个更简单的问题。

5. 发明授权

US6154868A Method and means for computationally efficient on-the-fly error correction in linear cyclic codes using ultra-fast error location 失效
标题翻译：用于使用超快速误差位置的线性循环码中计算高效的即时纠错的方法和装置
公开(公告)号：US6154868A
公开(公告)日：2000-11-28
申请号：US896348
申请日：1997-07-18
申请人： Charles Edwin Cox , Myron Dale Flickner , James Lee Hafner , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
发明人： Charles Edwin Cox , Myron Dale Flickner , James Lee Hafner , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/1545 , H03M13/1515 , H03M13/616
摘要： A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t.ltoreq.5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.
摘要翻译：一种计算有效的机器可实现的方法和装置，用于使用超快速错误位置处理在线性循环码的容量内即时检测和纠正接收到的码字中的错误。将来自码字综合征的有限伽罗瓦域的度t的每个误差定位多项式映射成表示与多项式系数相关的线性联立方程组的矩阵。指示码字内的错误位置的根通过对于t 5的所有根的修正的高斯消除过程从矩阵中提取，并且至少一个根加上来自用于迭代取代的有限域的候选根的子集，其中t> 5。单独确定校正后的值，并且通过将修正的值与由根表示的错误位置处的错误的码字值进行逻辑组合来确保校正。

6. 发明授权

US6141786A Method and apparatus for performing arithmetic operations on Galois fields and their extensions 失效
标题翻译：用于对伽罗瓦域及其扩展进行算术运算的方法和装置
公开(公告)号：US6141786A
公开(公告)日：2000-10-31
申请号：US90511
申请日：1998-06-04
申请人： Charles Edwin Cox , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
发明人： Charles Edwin Cox , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
IPC分类号： H03M13/15 , G11C29/00
CPC分类号： H03M13/158 , H03M13/15 , H03M13/1515
摘要： The invention relates to an arithmetic unit (AU) in combination with an algebraic block ECC decoder for controlling errors in an electronically recorded digital data message by performing at least one of a plurality of predetermined arithmetic operations on the data message in one or more of a plurality of subfields of a first GF(2.sup.12) or a second GF(2.sup.8) finite field. The arithmetic operations are selected either from a first group of operations associated with a first subfield GF(2.sup.4) as cubically extended to the first finite field GF(2.sup.12) or as quadratically extended to the second finite field GF(2.sup.8), or selected from a second group of operations associated with a second subfield GF(2.sup.6) as quadratically extended to the first finite field GF(2.sup.12).
摘要翻译：本发明涉及一种与代数块ECC解码器组合的算术单元（AU），用于通过对数字消息中的一个或多个中的数据消息执行多个预定算术运算中的至少一个来控制电子记录数字数据消息中的错误，第一GF（212）或第二GF（28）有限域的多个子场。算术运算从与第一子场GF（24）相关联的第一组运算中选择为立方式扩展到第一有限域GF（212）或二次扩展到第二有限域GF（28），或从与第二子场GF（26）相关联的第二组操作，其被二次扩展到第一有限域GF（212）。

7. 发明授权

US5638065A Maximum-likelihood symbol detection for RLL-coded data 失效
标题翻译： RLL编码数据的最大似然符号检测
公开(公告)号：US5638065A
公开(公告)日：1997-06-10
申请号：US489863
申请日：1995-06-13
申请人： Martin A. Hassner , Tetsuya Tamura , Shmuel Winograd
发明人： Martin A. Hassner , Tetsuya Tamura , Shmuel Winograd
IPC分类号： G11B20/10 , G11B20/14 , G11B20/18 , H03M7/00
CPC分类号： G11B20/1426 , G11B20/10009
摘要： Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.
摘要翻译： RLL编码信道中的模拟信号的并行ML处理，其中（1）信道的当前状态的向量和信道的下一状态的矢量使用模拟信号的沃尔什变换矢量系数来计算; （2）当前状态矢量和下一状态向量以及在模拟匹配滤波器中预先计算的矢量值用于产生与预选阈值进行比较的矢量标量积，用于产生在数字顺序有限状态机中使用的二进制判决输出以产生ML 符号决定（3）ML符号决定被反馈并用于从下一状态的向量中减去当前状态向量的符号间干扰值，以将下一状态向量变换为更新的当前状态向量。

8. 发明授权

US08640065B2 Circuit verification using computational algebraic geometry 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US08640065B2
公开(公告)日：2014-01-28
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

9. 发明申请

US20120005561A1 REDUCED CIRCUIT IMPLEMENTATION OF ENCODER AND SYNDROME GENERATOR 有权
标题翻译：编码器和综合发生器的减少电路实现
公开(公告)号：US20120005561A1
公开(公告)日：2012-01-05
申请号：US13168559
申请日：2011-06-24
申请人： Barry M. Trager , Shmuel Winograd
发明人： Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1515 , H03M13/1595
摘要： An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(28) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.
摘要翻译：错误校正方法和系统包括编码器和综合发生器，其并行操作以减少用于计算用于纠错码的校验符号和校正子的电路的数量。系统和方法一次计算对一致性的贡献和一次检查符号，而不是1个符号。因此，偶数综合征可以计算为奇数综合征的功率。此外，系统分配符号地址，使得对于具有72个符号的示例GF（28），具有不同于单位的立方根的三（3）个地址块，以允许数据符号被组合以减小大小和奇异综合征电路的复杂性。此外，用于产生检查符号的实现电路是使用校正位置的校正子矩阵的部分的倒数从校正子电路导出的。

10. 发明申请

US20100299576A1 System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码的误码率
公开(公告)号：US20100299576A1
公开(公告)日：2010-11-25
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

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