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1. 发明授权

US08406258B1 Apparatus and methods for low-jitter transceiver clocking 有权
标题翻译：低抖动收发器时钟的装置和方法
公开(公告)号：US08406258B1
公开(公告)日：2013-03-26
申请号：US12752984
申请日：2010-04-01
申请人： Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Sergey Shumarayev , Allen Chan
发明人： Wilson Wong , Tim Tri Hoang , Thungoc M. Tran , Sergey Shumarayev , Allen Chan
IPC分类号： H04J3/06
CPC分类号： H03M9/00 , H03K19/1776 , H04J3/047 , H04J3/0685
摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。还公开了其它实施例和特征。

2. 发明授权

US08290750B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US08290750B1
公开(公告)日：2012-10-16
申请号：US13036437
申请日：2011-02-28
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： H03F1/26
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

3. 发明授权

US08126079B1 High-speed serial data signal interface circuitry with multi-data-rate switching capability 有权
标题翻译：具有多数据速率切换功能的高速串行数据信号接口电路
公开(公告)号：US08126079B1
公开(公告)日：2012-02-28
申请号：US11824862
申请日：2007-07-03
申请人： Thungoc M. Tran , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Wilson Wong , Allen Chan
发明人： Thungoc M. Tran , Sergey Shumarayev , Tim Tri Hoang , Weiqi Ding , Wilson Wong , Allen Chan
IPC分类号： H04L27/00
CPC分类号： H04L7/033 , H03L7/22 , H04L7/0008
摘要： High-speed serial data signal transmitter and/or receiver circuitry is able to dynamically switch between handling data at two (or more) different data rates. Such a switch can be made very rapidly and with no requirement for reprogramming or reconfiguring the circuitry. Circuitry for glitchlessly switching between clock signals having different frequencies is also provided and may be used in the above-mentioned transmitter and/or receiver circuitry.
摘要翻译：高速串行数据信号发射机和/或接收机电路能够以两种（或多种）不同的数据速率在处理数据之间动态切换。这样的开关可以非常快速地进行，并且不需要重新编程或重新配置电路。还提供了用于在具有不同频率的时钟信号之间无差错地切换的电路，并且可以在上述发射机和/或接收机电路中使用。

4. 发明授权

US07899649B1 Signal detect for high-speed serial interface 有权
标题翻译：信号检测用于高速串行接口
公开(公告)号：US07899649B1
公开(公告)日：2011-03-01
申请号：US12053884
申请日：2008-03-24
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Thungoc M. Tran , Tim Tri Hoang , Weiqi Ding
IPC分类号： G06F19/00
CPC分类号： H03K5/19 , H03K19/1774 , H03K19/17744 , H03K19/1778
摘要： Signal detection circuitry for a serial interface oversamples the input—i.e., samples the input multiple times per clock cycle—so that the likelihood of missing a signal is reduced. Sampling may be done with a regenerative latch which has a large bandwidth and can latch a signal at high speed. The amplitude threshold for detection may be programmable, particularly in a programmable device. Thus, between the use of a regenerative latch which is likely to catch any signal that might be present, and the use of oversampling to avoid the problem of sampling at the wrong time, the likelihood of failing to detect a signal is greatly diminished. Logic, such as a state machine, may be used to determine whether the samples captured s do or do not represent a signal. That logic may be programmable, allowing a user to set various parameters for signal detection.
摘要翻译：串行接口的信号检测电路对输入进行过采样，即每个时钟周期对输入进行多次采样，从而减少信号丢失的可能性。可以使用具有大带宽的再生锁存器并且可以高速锁存信号来进行采样。用于检测的幅度阈值可以是可编程的，特别是在可编程器件中。因此，在可能捕获可能存在的任何信号的再生锁存器的使用之间以及使用过采样以避免在错误时间采样的问题，大大减少了不能检测信号的可能性。可以使用诸如状态机的逻辑来确定捕获的样本是否或不表示信号。该逻辑可以是可编程的，允许用户设置用于信号检测的各种参数。

5. 发明授权

US08175143B1 Adaptive equalization using data level detection 有权
标题翻译：使用数据级检测的自适应均衡
公开(公告)号：US08175143B1
公开(公告)日：2012-05-08
申请号：US12037284
申请日：2008-02-26
申请人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
发明人： Wilson Wong , Tin H. Lai , Allen Chan , Tim Tri Hoang , Sergey Shumarayev
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03356 , H04L2025/03745 , H04L2025/03783
摘要： A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.
摘要翻译：用于在自适应均衡中选择正确的均衡曲线的方法和电路使用反馈回路，其中输入的高速串行数据被数字化和反序列化以用于设备的其余部分，并且还被自适应状态机以提取用于数字化的参考电平并控制均衡曲线。参考电平的检测和均衡曲线的选择可以以不同的速率进行，以避免彼此干扰。状态机优选是可编程的。这在任何设备中是有用的，但是特别适用于诸如PLD或其他可编程集成电路设备的可编程设备，其中条件可以根据用户逻辑设计而变化。

6. 发明授权

US09246715B1 Pre-emphasis circuitry including a pre-emphasis voltage variation compensation engine 有权
标题翻译：预加重电路，包括预加重电压变化补偿引擎
公开(公告)号：US09246715B1
公开(公告)日：2016-01-26
申请号：US12432136
申请日：2009-04-29
申请人： Allen Chan , Wilson Wong , Tim Tri Hoang
发明人： Allen Chan , Wilson Wong , Tim Tri Hoang
IPC分类号： H03K19/094 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0272 , H03K19/00315 , H03K19/00361
摘要： A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit. Also, in one embodiment, the PVVC engine further includes an FIR delay circuit coupled to the digital FIR filter and a synchronizer circuit coupled to the digital FIR filter and the FIR delay circuit, where the FIR delay circuit introduces latency to match-delay produced by the transition detection circuit and the synchronizer circuit synchronizes data to be sent to the main driver, the pre-emphasis driver, and the compensation driver.
摘要翻译：一种预加重电路，其包括（1）具有转移检测电路的预加重电压变化补偿（PVVC）引擎和（2）耦合到PVVC引擎的补偿驱动器。在一个实施例中，补偿驱动器减少由预加重电路提供的预加重中的数据相关电压变化。在一个实施例中，响应于由PVVC引擎检测到的预定数据模式，补偿驱动器为预加重电路的性能关键电容性节点提供额外的提升。额外的升压会导致性能关键的电容性节点更快地充电或放电。在一个实施例中，PVVC引擎还包括耦合到转换检测电路的数字有限脉冲响应（FIR）滤波器。此外，在一个实施例中，PVVC引擎还包括耦合到数字FIR滤波器的FIR延迟电路和耦合到数字FIR滤波器和FIR延迟电路的同步器电路，其中FIR延迟电路将等待时间延迟到由转换检测电路和同步器电路将要发送到主驱动器，预加重驱动器和补偿驱动器的数据同步。

7. 发明授权

US08299802B2 Method to digitize analog signals in a system utilizing dynamic analog test multiplexer for diagnostics 有权
标题翻译：使用动态模拟测试多路复用器对系统中的模拟信号进行数字化的方法进行诊断
公开(公告)号：US08299802B2
公开(公告)日：2012-10-30
申请号：US12263290
申请日：2008-10-31
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev
IPC分类号： G01R31/02
CPC分类号： G01R31/3167
摘要： An integrated circuit capable of monitoring analog voltages inside an analog block is presented. The integrated circuit has an analog test multiplexer (mux) whose inputs are connected to analog voltages of interest inside an analog block. The analog test multiplexer directs a selected analog voltage from an analog block to the output of the analog test mux. The integrated circuit further includes an analog monitor state machine which provides the selection bits to the analog test multiplexer, enabling random access to the analog voltages inside the analog block. The integrated circuit also includes an analog to digital converter for converting the selected analog voltage from the analog test multiplexer into a digital representation.
摘要翻译：提出了一种能够监视模拟模块内的模拟电压的集成电路。集成电路具有模拟测试复用器（多路复用器），其输入端连接到模拟模块内的感兴趣的模拟电压。模拟测试复用器将选定的模拟电压从模拟模块引导到模拟测试复用器的输出。集成电路还包括模拟监视状态机，其向模拟测试多路复用器提供选择位，使得能够随机访问模拟块内的模拟电压。集成电路还包括用于将来自模拟测试多路复用器的所选模拟电压转换为数字表示的模数转换器。

8. 发明授权

US08184651B2 PLD architecture optimized for 10G Ethernet physical layer solution 有权
标题翻译：针对10G以太网物理层解决方案优化的PLD架构
公开(公告)号：US08184651B2
公开(公告)日：2012-05-22
申请号：US12100360
申请日：2008-04-09
申请人： Allen Chan , Sergey Shumarayev , Wilson Wong , Weiqi Ding
发明人： Allen Chan , Sergey Shumarayev , Wilson Wong , Weiqi Ding
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L49/352
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
摘要翻译：集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

9. 发明授权

US07834712B2 Techniques for providing option conductors to connect components in an oscillator circuit 有权
标题翻译：提供选项导体以连接振荡器电路中的组件的技术
公开(公告)号：US07834712B2
公开(公告)日：2010-11-16
申请号：US12277810
申请日：2008-11-25
申请人： Sergey Shumarayev , Wilson Wong , Allen Chan , Ali Atesoglu
发明人： Sergey Shumarayev , Wilson Wong , Allen Chan , Ali Atesoglu
IPC分类号： H03B5/00
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1243 , H03B5/1265 , H03B2201/011
摘要： An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.
摘要翻译：振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。

10. 发明授权

US08385496B1 Apparatus and methods of receiver offset calibration 有权
标题翻译：接收机偏移校准的装置和方法
公开(公告)号：US08385496B1
公开(公告)日：2013-02-26
申请号：US12909744
申请日：2010-10-21
申请人： Allen Chan , Wilson Wong , Sergey Shumarayev
发明人： Allen Chan , Wilson Wong , Sergey Shumarayev
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L7/033
摘要： One embodiment relates to a method of offset cancellation for a receiver in an integrated circuit. The receiver is set to a phase-detector offset-cancellation mode so as to determine offset cancellation settings for the phase detector. The offset cancellation settings are applied to the phase detector. The receiver is then set to a receiver-driver offset-cancellation mode so as to determine an offset cancellation setting for the receiver driver. This offset cancellation setting is applied to the receiver driver. Another embodiment relates to an integrated circuit configured to perform receiver offset cancellation. The integrated circuit including a receiver driver configured to receive a differential input signal, a phase detector including a plurality of latches, a calibration controller, a voltage source, and first and second pairs of switches. Other embodiments, aspects, and features are also disclosed.
摘要翻译：一个实施例涉及一种用于集成电路中的接收机的偏移抵消的方法。接收机设置为相位检测器偏移消除模式，以便确定相位检测器的偏移消除设置。偏移消除设置被应用于相位检测器。然后将接收机设置为接收器 - 驱动器偏移消除模式，以便确定接收器驱动器的偏移消除设置。该偏移消除设置被应用于接收器驱动器。另一实施例涉及被配置为执行接收机偏移消除的集成电路。该集成电路包括被配置为接收差分输入信号的接收器驱动器，包括多个锁存器的相位检测器，校准控制器，电压源以及第一和第二对开关。还公开了其它实施例，方面和特征。

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