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1. 发明授权

US09608676B2 Digital pre-distortion systems in transmitters 有权
公开(公告)号：US09608676B2
公开(公告)日：2017-03-28
申请号：US13940263
申请日：2013-07-12
申请人： ANALOG DEVICES TECHNOLOGY
发明人： Dong Chen
IPC分类号： H04B1/04 , H03F1/32 , H03F3/195 , H03F3/24
CPC分类号： H04B1/0475 , H03F1/3247 , H03F1/3258 , H03F1/3282 , H03F3/195 , H03F3/245 , H03F2200/111 , H03F2201/3206 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H04B2001/0425
摘要： Various digital pre-distortion systems for use in transmitters are disclosed. The digital pre-distortion system comprises an observing path, which performs either undersampling or radio frequency sampling of the output of a power amplifier. Undersampling may be performed at a rate, which causes aliasing to occur in the undersampled frequency domain. Both undersampling and radio frequency sampling reduces the complexity of the digital pre-distortion system by removing any down mixing modules or anti-aliasing modules, while maintaining reasonable performance of the digital pre-distortion systems.

2. 发明授权

US09460016B2 Cache way prediction 有权
标题翻译：缓存方式预测
公开(公告)号：US09460016B2
公开(公告)日：2016-10-04
申请号：US14306162
申请日：2014-06-16
申请人： ANALOG DEVICES TECHNOLOGY
发明人： John L. Redford , Michael G. Perkins
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0864 , G06F12/0895 , Y02D10/13
摘要： In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation.
摘要翻译：在一个示例中，提供了一种系统和方法，用于基于由指定地址寄存器访问的最后方式（如果可用）来预测所请求的存储器地址最有可能保持在多路高速缓存中的方式。如果不可用，则系统可以确定没有可用的最佳预测。在这种情况下，读取每种方式，忽略多余的值，或者根据需要执行缓存填充。在某些实施例中，只有加法运算的最低有效位的一部分用于基加 - 偏移寻址模式中的方式预测。这使得能够在全宽加法完成之前进行判定，从而通过预测操作不会不必要地延长时钟周期长度。

3. 发明授权

US09438127B2 Reverse current control for an isolated power supply having synchronous rectifiers 有权
标题翻译：具有同步整流器的隔离电源的反向电流控制
公开(公告)号：US09438127B2
公开(公告)日：2016-09-06
申请号：US13947820
申请日：2013-07-22
申请人： ANALOG DEVICES TECHNOLOGY
发明人： Yingyang Ou , Qingyi Huang , Renjian Xie , Ling Ren
IPC分类号： H02M3/335
CPC分类号： H02M3/33592 , Y02B70/1475
摘要： In certain example embodiments, a system is provided that includes a circuit. The system also includes a reverse current control module that provides an isolated power supply in order to protect one or more devices in a power chain during one or more testing activities having one or more requirements.
摘要翻译：在某些示例性实施例中，提供了包括电路的系统。该系统还包括反向电流控制模块，其提供隔离的电源，以便在具有一个或多个要求的一个或多个测试活动期间保护功率链中的一个或多个设备。

4. 发明授权

US09373007B2 Low-cost capacitive sensing decoder 有权
标题翻译：低成本电容式感应解码器
公开(公告)号：US09373007B2
公开(公告)日：2016-06-21
申请号：US14086793
申请日：2013-11-21
申请人： ANALOG DEVICES TECHNOLOGY
发明人： Joseph Wayne Palmer , Paul Vincent Errico , Liam Patrick Riordan , Juan Francisco Escobar Valero
IPC分类号： G06K7/08 , G06K19/067
CPC分类号： G06K7/081 , G06K19/067
摘要： A low-cost system comprising a pattern arranged to encode information and a decoder for decoding the information encoded in the pattern is described. In particular, the mechanism employs a capacitive sensing technique. Electrodes are arranged (or stimulated, during operation) to each generate an electric field, and sense disturbances on the electric field caused by the pattern when the pattern is positioned over the electrodes. The spatial arrangement of the pattern allows information to be encoded on a strip or surface and decoded by capacitive sensors arranged to detect disturbances caused by possible patterns. The resulting solution is cheaper and less complex than optical solutions, e.g., barcodes and optical barcode readers. The mechanism may be used in a glucose meter for encoding and decoding an identifier for distinguishing batches of glucose meter test strips.
摘要翻译：描述了一种低成本系统，其包括布置成编码信息的模式和用于解码在模式中编码的信息的解码器。特别地，该机构采用电容感测技术。电极被布置（或在操作期间被刺激）以产生电场，并且当图案位于电极上方时，感测由图案引起的电场上的扰动。模式的空间排列允许将信息编码在条带或表面上，并通过布置成检测由可能图案引起的干扰的电容传感器进行解码。所得到的解决方案比诸如条形码和光学条形码读取器的光学解决方案更便宜并且更不复杂。该机制可以用于葡萄糖计中，用于编码和解码用于区分葡萄糖计测试条的批次的标识符。

5. 发明授权

US09349386B2 System and method for processor wake-up based on sensor data 有权
标题翻译：基于传感器数据的处理器唤醒的系统和方法
公开(公告)号：US09349386B2
公开(公告)日：2016-05-24
申请号：US13788062
申请日：2013-03-07
申请人： ANALOG DEVICES TECHNOLOGY
发明人： Robert Adams , Maikael Mortensen
IPC分类号： G10L11/06 , G10L21/06 , G10L25/93 , G10L25/48 , G06F1/32 , G10L25/84 , G10L25/87 , G10L25/78 , G10L15/08 , G10L15/28
CPC分类号： G10L21/06 , G06F1/3206 , G10L15/28 , G10L25/48 , G10L25/78 , G10L25/84 , G10L25/87 , G10L25/93 , G10L2015/088 , G10L2025/783 , G10L2025/786
摘要： A system for processor wake-up based on sensor data includes an audio buffer, an envelope buffer, and a processor. The audio buffer is configured to store a first data from a sensor. The first data is generated according to a first sampling rate. The envelope buffer is configured to store a second data, which is derived from the first data according to a second sampling rate, which is less than the first sampling rate. The processor is configured to wake up periodically from an idle state and read the second data from the envelope buffer. If the second data indicates an activity, the processor is configured to read the first data from the audio buffer. If the second data does not indicate an activity, the processor is configured to return to the idle state.
摘要翻译：基于传感器数据的用于处理器唤醒的系统包括音频缓冲器，包络缓冲器和处理器。音频缓冲器被配置为存储来自传感器的第一数据。根据第一采样率产生第一数据。包络缓冲器被配置为存储第二数据，其根据小于第一采样率的第二采样率从第一数据导出。处理器被配置为周期性地从空闲状态唤醒并从包络缓冲器读取第二数据。如果第二数据指示活动，则处理器被配置为从音频缓冲器读取第一数据。如果第二个数据不表示活动，则处理器被配置为返回到空闲状态。

6. 发明申请

US20160105194A1 PASSIVE ANALOG SAMPLE AND HOLD IN ANALOG-TO-DIGITAL CONVERTERS 审中-公开
标题翻译：被动模拟样品并保存在模拟数字转换器中
公开(公告)号：US20160105194A1
公开(公告)日：2016-04-14
申请号：US14511613
申请日：2014-10-10
申请人： ANALOG DEVICES TECHNOLOGY
发明人： MAHESH MADHAVAN KUMBARANTHODIYIL , Sandeep Monangi
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/122 , H03M1/466
摘要： In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors.
摘要翻译：在示例实施例中，提供了一种促进被动模拟采样和保持的模数转换器（ADC），并且包括一对二进制加权转换电容器阵列，一对采样电容器和配置每个转换电容器阵列的多个开关用于采样相位的采样电容器，电荷转移阶段和位试验阶段。在采样阶段，采样电容器与转换电容器分离并耦合到模拟输入电压。在电荷转移阶段期间，采样电容器耦合到转换电容器并与模拟输入电压分离。在位试验阶段，采样电容器与转换电容器分离。

7. 发明申请

US20160099692A1 HIGH GAIN, HIGH SLEW RATE AMPLIFIER 有权
标题翻译：高增益，高速率放大器
公开(公告)号：US20160099692A1
公开(公告)日：2016-04-07
申请号：US14504540
申请日：2014-10-02
申请人： ANALOG DEVICES TECHNOLOGY
发明人： VINAYAK MUKUND KULKARNI
IPC分类号： H03F3/16
CPC分类号： H03F3/45183 , H03F2203/45248 , H03F2203/45626 , H03F2203/45644 , H03F2203/45646
摘要： In an example embodiment, an amplifier having high gain and high slew rate is provided and includes a pair of input transistors to which input voltage is applied, a pair of diode-connected loads coupled to the input transistors, at least one pair of current sources coupled to the diode-connected loads, and a bias control configured to turn off the at least one pair of current sources to enable high slew rate for the amplifier and to turn on the at least one pair of current sources to enable high gain for the amplifier. In specific embodiments, the current sources include transistors, the bias control controls a bias voltage to the current sources, and the bias voltage is driven to the supply voltage (VDD) to turn off the current sources.
摘要翻译：在示例实施例中，提供了具有高增益和高转换速率的放大器，并且包括一对输入电压施加到的输入晶体管，耦合到输入晶体管的一对二极管连接的负载，至少一对电流源耦合到所述二极管连接的负载，以及偏置控制，被配置为关断所述至少一对电流源，以使所述放大器能够实现高转换速率，并且接通所述至少一对电流源，以使所述至少一对电流源能够获得高增益放大器在具体实施例中，电流源包括晶体管，偏置控制控制到电流源的偏置电压，偏置电压被驱动到电源电压（VDD）以截止电流源。

8. 发明授权

US09298988B2 Support vector machine based object detection system and associated method 有权
标题翻译：基于支持向量机的对象检测系统及相关方法
公开(公告)号：US09298988B2
公开(公告)日：2016-03-29
申请号：US14076030
申请日：2013-11-08
申请人： ANALOG DEVICES TECHNOLOGY
发明人： Prasanna Baja Thirumaleshwara , Vijaykumar Nagarajan
IPC分类号： G06K9/00 , G06K9/46 , G06K9/62 , G06T11/60
CPC分类号： G06K9/00624 , G06K9/4604 , G06K9/4642 , G06K9/6267 , G06K9/6269 , G06N99/005 , G06T11/60
摘要： An exemplary object detection method includes generating feature block components representing an image frame, and analyzing the image frame using the feature block components. For each feature block row of the image frame, feature block components associated with the feature block row are evaluated to determine a partial vector dot product for detector windows that overlap a portion of the image frame including the feature block row, such that each detector window has an associated group of partial vector dot products. The method can include determining a vector dot product associated with each detector window based on the associated group of partial vector dot products, and classifying an image frame portion corresponding with each detector window as an object or non-object based on the vector dot product. Each feature block component can be moved from external memory to internal memory once implementing the exemplary object detection method.
摘要翻译：示例性对象检测方法包括生成表示图像帧的特征块分量，以及使用特征块分量来分析图像帧。对于图像帧的每个特征块行，评估与特征块行相关联的特征块分量，以确定与包括特征块行的图像帧的一部分重叠的检测器窗口的部分矢量点积，使得每个检测器窗口具有相关组的部分矢量点积。该方法可以包括基于相关组的部分矢量点积来确定与每个检测器窗口相关联的矢量点积，并且基于矢量点积将对应于每个检测器窗口的图像帧部分分类为对象或非对象。一旦实现了示例性对象检测方法，每个特征块组件可以从外部存储器移动到内部存储器。

9. 发明申请

US20160072275A1 EMBEDDED OVERLOAD PROTECTION IN DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTERS 有权
标题翻译： DELTA-SIGMA模拟数字转换器嵌入式过载保护
公开(公告)号：US20160072275A1
公开(公告)日：2016-03-10
申请号：US14477236
申请日：2014-09-04
申请人： ANALOG DEVICES TECHNOLOGY
发明人： TREVOR CLIFFORD CALDWELL , COREY PETERSEN , DAVID NELSON ALLDRED , HAJIME SHIBATA
IPC分类号： H02H7/12 , H03M3/00
CPC分类号： H02H7/12 , H03M3/30 , H03M3/36 , H03M3/464 , H03M3/484
摘要： Delta-sigma modulators do not handle overload well, and often become unstable if the input goes beyond the full-scale range of the modulator. To provide overload protection, an improved technique embeds an overload detector in the delta sigma modulator. When an overload condition is detected, coefficient(s) of the delta sigma modulator is adjusted to accommodate for the overloaded input. The improved technique advantageously allows the delta sigma modulator to handle overload gracefully without reset, and offers greater dynamic range at reduced resolution. Furthermore, the coefficient(s) of the delta sigma modulator can be adjusted in such a way to ensure the noise transfer function is not affected.
摘要翻译： Δ-Σ调制器不能很好地处理过载，如果输入超出调制器的满量程范围，通常会变得不稳定。为了提供过载保护，改进的技术将过载检测器嵌入到Δ-Σ调制器中。当检测到过载条件时，调节ΔΣ调制器的系数以适应过载输入。改进的技术有利地允许Δ-Σ调制器在没有复位的情况下优雅地处理过载，并且以降低的分辨率提供更大的动态范围。此外，可以以这样的方式调整Δ-Σ调制器的系数，以确保噪声传递函数不受影响。

10. 发明申请

US20150357982A1 GAIN BOOSTED DIFFERENTIAL TRANSCONDUCTANCE AMPLIFIER 有权
标题翻译：增益差分平衡放大器
公开(公告)号：US20150357982A1
公开(公告)日：2015-12-10
申请号：US14296247
申请日：2014-06-04
申请人： Analog Devices Technology
发明人： EBERHARD BRUNNER
IPC分类号： H03G1/00 , H03F3/04
CPC分类号： H03G1/0017 , H03F3/04 , H03F3/45 , H03F3/45085 , H03F2203/45274 , H03F2203/45392 , H03F2203/45601 , H03F2203/45612 , H03G1/0023
摘要： A transconductance gain stage including a pair of gain transistors, each gain transistor having a base and an emitter, the emitter of each gain transistor electrically coupled to a degenerating resistor, and the emitter of each gain transistor connected to a gain resistor.
摘要翻译：跨导增益级包括一对增益晶体管，每个增益晶体管具有基极和发射极，每个增益晶体管的发射极电耦合到退化电阻器，并且每个增益晶体管的发射极连接到增益电阻器。

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