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1. 发明申请

US20180234103A1 DEVICE AND METHOD FOR REQUESTING AN ANALOG-TO-DIGITAL CONVERSION 审中-公开
公开(公告)号：US20180234103A1
公开(公告)日：2018-08-16
申请号：US15895453
申请日：2018-02-13
申请人： Infineon Technologies AG
发明人： Jens Barrenscheen , Peter Bogner , Juergen Schaefer
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H02M3/33546 , H02P27/06 , H03M1/0624 , H03M1/122
摘要： An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.

2. 发明授权

US09791482B1 Power integrated circuit with autonomous limit checking of ADC channel measurements 有权
公开(公告)号：US09791482B1
公开(公告)日：2017-10-17
申请号：US15607683
申请日：2017-05-30
申请人： Active-Semi, Inc.
发明人： John H. Carpenter, Jr. , Brett E. Smith , Hiroshi Watanabe
IPC分类号： H01H85/00 , G01R19/25 , G05B15/02 , G05F1/66 , G05B11/28 , H02M1/08 , H02H3/08
CPC分类号： H02M1/32 , G01R19/2513 , G01R31/362 , G05B11/28 , G05B15/02 , G05F1/66 , H01H85/0241 , H02H3/08 , H02J9/061 , H02M1/08 , H02M3/156 , H02M3/158 , H02M3/1582 , H02M3/1588 , H02M2001/0009 , H03M1/122 , H03M1/765
摘要： A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.

3. 发明授权

US09706143B2 Readout circuit and method of using the same 有权
公开(公告)号：US09706143B2
公开(公告)日：2017-07-11
申请号：US14947554
申请日：2015-11-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yuichiro Yamashita
IPC分类号： H03M1/12 , H04N5/357 , H04N5/367 , H04N5/378 , H03M1/00 , H01L27/146 , H04N9/04 , H04N5/335 , H03M1/16 , H03M3/00
CPC分类号： H04N5/357 , H01L27/14643 , H03M1/00 , H03M1/12 , H03M1/1205 , H03M1/122 , H03M1/168 , H03M3/462 , H03M3/466 , H04N5/335 , H04N5/367 , H04N5/378 , H04N9/045
摘要： A readout circuit includes a first analog circuit configured to receive an output of a first sub-array of a pixel array and to output a first signal based on the received output of the first sub-array. A second analog circuit is configured to receive an output of a second sub-array of the pixel array and to output a second signal based on the received output of the second sub-array. A first digital circuit is configured to receive the first signal and convert the first signal to a first digital signal, and receive the second signal and convert the second signal to a second digital signal.

4. 发明授权

US09705402B1 Power loss protection integrated circuit 有权
公开(公告)号：US09705402B1
公开(公告)日：2017-07-11
申请号：US15201265
申请日：2016-07-01
申请人： Active-Semi, Inc.
发明人： John H. Carpenter, Jr. , Brett E. Smith , Hiroshi Watanabe
IPC分类号： H02M3/158 , H02M1/32 , H02M1/08 , H02M3/156 , H02M1/00
CPC分类号： H02M1/32 , G01R19/2513 , G01R31/362 , G05B11/28 , G05B15/02 , G05F1/66 , H01H85/0241 , H02H3/08 , H02J9/061 , H02M1/08 , H02M3/156 , H02M3/158 , H02M3/1582 , H02M3/1588 , H02M2001/0009 , H03M1/122 , H03M1/765
摘要： A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.

5. 发明授权

US09323226B1 Sub-ranging voltage-to-time-to-digital converter 有权
标题翻译：子范围电压 - 时间 - 数字转换器
公开(公告)号：US09323226B1
公开(公告)日：2016-04-26
申请号：US14979186
申请日：2015-12-22
申请人： IQ-Analog Corporation
发明人： Mikko Waltari
IPC分类号： H03M1/12 , G04F10/00 , H03K4/08
CPC分类号： G04F10/005 , G04F10/105 , H03K4/08 , H03M1/1042 , H03M1/122 , H03M1/1295 , H03M1/14 , H03M1/361 , H03M1/56
摘要： A system and method are provided for converting voltage-to-time-to-digital signals. The method periodically samples a continuous analog input and discharges the sampled analog input at a predetermined rate to supply a continuous analog ramp signal. The ramp signal is converted into an n-bit coded digital word representing the q most significant bits (MSBs) of a k-bit binary word, where q is an integer greater than 0, n is an integer greater than 1, and k is an integer greater than q. At least one bit of the coded digital word is supplied at a time representing the p least significant bits (LSBs) of the k-bit binary word. The coded digital word is converted into a single-bit pulse signal containing timing information representing the p LSBs of the k-bit binary word at an output, and the timing information is converted into the p LSBs of the k-bit binary word.
摘要翻译：提供了一种用于转换电压 - 时间 - 数字信号的系统和方法。该方法周期性地采样连续的模拟输入，并以预定的速率对采样的模拟输入进行放电，以提供连续的模拟斜坡信号。斜坡信号被转换成表示k位二进制字的q个最高有效位（MSB）的n位编码数字字，其中q是大于0的整数，n是大于1的整数，并且k是大于q的整数。在代表k位二进制字的p个最低有效位（LSB）的时间，提供编码数字字的至少一位。编码数字字被转换为包含表示输出端的k位二进制字的p个LSB的定时信息的单位脉冲信号，并将定时信息转换成k位二进制字的p个LSB。

6. 发明授权

US09246506B2 Semiconductor integrated circuit device and data processing system 有权
公开(公告)号：US09246506B2
公开(公告)日：2016-01-26
申请号：US14628101
申请日：2015-02-20
申请人： Renesas Electronics Corporation
发明人： Fumiki Kawakami , Naoki Yada , Hiroyuki Tsunakawa
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1205 , H03K5/14 , H03M1/00 , H03M1/12 , H03M1/122 , H03M1/1225
摘要： The semiconductor integrated circuit device has: more than one analog port; an A/D conversion part operable to execute an A/D conversion process for converting an analog signal taken in through each analog port into a digital signal for each preset virtual channel; and an A/D conversion control part operable to control an action of the A/D conversion part. The A/D conversion control part includes: virtual channel registers on which correspondence between the virtual channel and the analog port can be set; and a scan-group-forming register on which a start position of a scan group and an end position thereof can be set. The A/D conversion control part controls the A/D conversion part to successively execute an A/D conversion process on a plurality of virtual channels from a virtual channel associated with the start pointer to a virtual channel associated with the end pointer.

7. 发明申请

US20150333763A1 READOUT CIRCUIT AND METHOD OF USING THE SAME 有权
标题翻译：读出电路及其使用方法
公开(公告)号：US20150333763A1
公开(公告)日：2015-11-19
申请号：US14277487
申请日：2014-05-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yuichiro YAMASHITA
IPC分类号： H03M1/12
CPC分类号： H04N5/357 , H01L27/14643 , H03M1/00 , H03M1/12 , H03M1/1205 , H03M1/122 , H03M1/168 , H03M3/462 , H03M3/466 , H04N5/335 , H04N5/367 , H04N5/378 , H04N9/045
摘要： A readout circuit includes a first analog circuit for receiving an output of a first sub-array of a pixel array, wherein the first analog circuit is configured to output a first analog signal. The readout circuit further includes a second analog circuit for receiving an output of a second sub-array of the pixel array, wherein the second sub-array comprises at least one pixel on a same row of the pixel array as at least one pixel of the first sub-array, and the second analog circuit is configured to output a second analog signal. The readout circuit further includes a first digital circuit for receiving the first analog signal and to convert the first analog signal to a first digital signal, wherein the first digital circuit is further configured to receive the second analog signal and to convert the second analog signal to a second digital signal.
摘要翻译：读出电路包括用于接收像素阵列的第一子阵列的输出的第一模拟电路，其中第一模拟电路被配置为输出第一模拟信号。读出电路还包括第二模拟电路，用于接收像素阵列的第二子阵列的输出，其中第二子阵列包括与像素阵列的至少一个像素在像素阵列相同的行上的至少一个像素第一子阵列，并且第二模拟电路被配置为输出第二模拟信号。读出电路还包括用于接收第一模拟信号并将第一模拟信号转换为第一数字信号的第一数字电路，其中第一数字电路还被配置为接收第二模拟信号并将第二模拟信号转换为第二个数字信号。

8. 发明申请

US20120299760A1 SEQUENCE ARBITER FOR ANALOG-TO-DIGITAL CONVERSIONS 有权
标题翻译：用于模拟数字转换的序列ARBITER
公开(公告)号：US20120299760A1
公开(公告)日：2012-11-29
申请号：US13467564
申请日：2012-05-09
申请人： Gianluigi Forte , Stello Matteo Bille' , Dino Costanzo
发明人： Gianluigi Forte , Stello Matteo Bille' , Dino Costanzo
IPC分类号： H03M1/12
CPC分类号： H03M1/122
摘要： An analog-to-digital converter device may include an input multiplexer circuit having analog input terminals configured to receive a respective plurality of analog input signals. The input multiplexer circuit may be responsive to a first select input. The device may also include a trigger multiplexer circuit having input terminals configured to receive respective triggering signals. The trigger multiplexer circuit may be responsive to a second select input. Analog-to-digital converter circuitry may be configured to convert the selected analog signal into a digital signal. A sequence arbiter may be coupled to the first and second select inputs and may have input terminals configured to receive a respective plurality of conversion sequence configuration signals. The sequence arbiter may be configured to manage each conversion sequence of the analog-to-digital converter circuitry based upon the relative conversion sequence configuration signal received, and control the conversion sequences.
摘要翻译：模拟 - 数字转换器装置可以包括具有被配置为接收相应的多个模拟输入信号的模拟输入端的输入多路复用器电路。输入多路复用器电路可以响应于第一选择输入。该装置还可以包括具有被配置为接收相应的触发信号的输入端的触发多路复用器电路。触发多路复用器电路可以响应于第二选择输入。模数转换器电路可以被配置为将所选择的模拟信号转换为数字信号。序列仲裁器可以耦合到第一和第二选择输入，并且可以具有被配置为接收相应的多个转换序列配置信号的输入端子。序列仲裁器可以被配置为基于接收到的相对转换序列配置信号来管理模数转换器电路的每个转换序列，并且控制转换序列。

9. 发明申请

US20120075135A1 Analog-Digital Conversion 有权
标题翻译：模拟数字转换
公开(公告)号：US20120075135A1
公开(公告)日：2012-03-29
申请号：US13236417
申请日：2011-09-19
申请人： Lourans Samid , Johannes Schaefer , Thomas Janz
发明人： Lourans Samid , Johannes Schaefer , Thomas Janz
IPC分类号： H03M1/12
CPC分类号： H03M1/122
摘要： In one embodiment, a method includes receiving a first analog signal at a first input; receiving a second analog signal at a second input; mixing the first analog signal with a first oscillator signal having a first frequency; mixing the second analog signal with a second oscillator signal having a second frequency; converting a sum signal to a digital signal; generating a first control signal based on a first digital value of a first function and the digital signal; and generating a second control signal based on a second digital value of a second function and the digital signal.
摘要翻译：在一个实施例中，一种方法包括：在第一输入处接收第一模拟信号; 在第二输入处接收第二模拟信号; 将第一模拟信号与具有第一频率的第一振荡器信号混合; 将第二模拟信号与具有第二频率的第二振荡器信号混合; 将和信号转换为数字信号; 基于第一功能的第一数字值和数字信号产生第一控制信号; 以及基于第二功能和数字信号的第二数字值产生第二控制信号。

10. 发明授权

US08059758B2 Conversion of multiple analog signals in an analog to digital converter 有权
标题翻译：在模数转换器中转换多个模拟信号
公开(公告)号：US08059758B2
公开(公告)日：2011-11-15
申请号：US11352495
申请日：2006-02-10
申请人： Daniel F. Filipovic
发明人： Daniel F. Filipovic
IPC分类号： H04L27/00
CPC分类号： H03M3/472 , H03M1/122
摘要： A multiple analog signal converter (100) simultaneously converts multiple analog signals (104,106) to digital signals (112, 114) using a single analog to digital converter (ADC) 102. A first analog signal (104) at a first center frequency and a second analog signal (106) at a second center frequency are processed by the ADC (102) to generate a composite digital signal (110) comprising a first digital signal (112) corresponding to the first analog signal (104) and a second digital signal (114) corresponding to the second analog signal (106). The composite digital signal (110) is digitally frequency shifted to recover the second digital signal (106). The first digital signal (104) is recovered by digitally filtering the composite digital signal (110). In some circumstances, a first radio frequency (RF) signal (118) and a second RF signal (122) are frequency shifted to generate the first analog signal (104) and second analog signal (106).
摘要翻译：多模拟信号转换器（100）使用单个模数转换器（ADC）102同时将多个模拟信号（104,106）转换为数字信号（112,114）。第一中心频率的第一模拟信号（104）和在第二中心频率处的第二模拟信号（106）由ADC（102）处理以产生包括对应于第一模拟信号（104）的第一数字信号（112）和第二数字信号（104）的复合数字信号（114）对应于第二模拟信号（106）。复合数字信号（110）被数字频移以恢复第二数字信号（106）。通过数字滤波复合数字信号（110）来恢复第一数字信号（104）。在某些情况下，第一射频（RF）信号（118）和第二RF信号（122）被频移以产生第一模拟信号（104）和第二模拟信号（106）。

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