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1. 发明申请

US20090094571A1 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US20090094571A1
公开(公告)日：2009-04-09
申请号：US12315998
申请日：2008-12-09
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。。。 xN，并输出命令和数据的顺序。

2. 发明授权

US07380223B2 Method and system for converting netlist of integrated circuit between libraries 失效
标题翻译：图书馆集成电路网表的转换方法及系统
公开(公告)号：US07380223B2
公开(公告)日：2008-05-27
申请号：US11257206
申请日：2005-10-24
申请人： Pavel Panteleev , Andrey A. Nikitin , Alexander E. Andreev
发明人： Pavel Panteleev , Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method for converting a netlist of an integrated circuit from a first library to a second library. The first library may include logic cells AND, OR and NOT, and the second library may include logic cells NAND and NOR. The method includes steps as follows. Logic cells of the netlist are topologically sorted from outputs to inputs. AND and OR cells of the netlist are replaced with NOT, NAND and NOR cells. Simplification of the netlist is performed in a topological order.
摘要翻译：本发明提供一种用于将集成电路的网表从第一库转换为第二库的方法。第一个库可以包括逻辑单元AND，OR和NOT，并且第二库可以包括逻辑单元NAND和NOR。该方法包括以下步骤。网表的逻辑单元从输出到输入进行拓扑分类。将网表的AND和OR单元替换为NOT，NAND和NOR单元。网表的简化是以拓扑顺序执行的。

3. 发明授权

US07219321B2 Process and apparatus for memory mapping 有权
标题翻译：内存映射的过程和设备
公开(公告)号：US07219321B2
公开(公告)日：2007-05-15
申请号：US10830739
申请日：2004-04-25
申请人： Andrey A. Nikitin , Alexander E. Andreev , Anatoli A. Bolotov
发明人： Andrey A. Nikitin , Alexander E. Andreev , Anatoli A. Bolotov
IPC分类号： G06F9/45 , G06F17/50 , H03K17/693 , H03K19/00
CPC分类号： G06F12/02 , G06F17/5045
摘要： A plurality of user-defined memories are mapped to pre-defined basic memories, such as defined on a base platform. The user-defined memories are dividing into classes of similar memories. A mapping technique is selected for members of a selected class of user-defined memories that minimizes the ratio (maxi,j(USEDi,j/AVAILi,j)) of basic memories that have been mapped to basic memories that are available for mapping. If the number of different memory mappings is smaller than a threshold the mapping technique is applied to each user-defined memory. If the number of different memory mappings is greater than the threshold, the groups are arranged in ordered queues of single memory types based on a mapping price and the mapping technique is selected based on a memory of each group and is applied to each user-defined memory in the respective group.
摘要翻译：多个用户定义的存储器映射到预定义的基本存储器，诸如在基础平台上定义的。用户定义的存储器被分成类似的存储器的类别。为选定类别的用户定义的存储器的成员选择映射技术，其使比率最小化（最大值，最小化，最小化，最小化，j））已被映射到可用于映射的基本存储器的基本存储器。如果不同的存储器映射的数量小于阈值，则映射技术被应用于每个用户定义的存储器。如果不同内存映射的数量大于阈值，则基于映射价格将组排列成单个存储器类型的有序队列，并且基于每个组的存储器选择映射技术并将其应用于每个用户定义记忆在相应的组。

4. 发明授权

US07168052B2 Yield driven memory placement system 有权
标题翻译：产量驱动记忆放置系统
公开(公告)号：US07168052B2
公开(公告)日：2007-01-23
申请号：US10875128
申请日：2004-06-23
申请人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
发明人： Alexander E. Andreev , Andrey A. Nikitin , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F9/45 , H03K17/693 , H03K19/00
CPC分类号： G06F17/5045 , G06F12/0292 , G06Q10/0875 , G06Q99/00
摘要： A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.
摘要翻译：用户定义的存储器设计被映射到用于IC的基础平台的存储器，该存储器包含多个存储器组，每个存储器组包含预定类型的多个存储器。从设计的多个存储器集合中选择最佳存储器集合，其基于设计及其与IC的部分的连接，从多个集合中选择每个存储器组的偏好率，并且将该设计选择性地分配给基于优先级的内存集。通过定义所选择的存储器组中的每个顾客存储器的位置的索引，将设计最佳地映射到所选存储器组的多个存储器。所选择的存储器组中的客户存储器按顺序排列，并且所选择的存储器组的连续数量的存储器按顺序分配给每个客户存储器。

5. 发明授权

US06901573B2 Method for evaluating logic functions by logic circuits having optimized number of and/or switches 失效
公开(公告)号：US06901573B2
公开(公告)日：2005-05-31
申请号：US10382036
申请日：2003-03-05
申请人： Andrey A. Nikitin , Alexander E. Andreev
发明人： Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F17/10 , G06F17/50
CPC分类号： G06F17/505
摘要： A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.

6. 发明授权

US06615401B1 Blocked net buffer insertion 有权
标题翻译：阻塞的网络缓冲区插入
公开(公告)号：US06615401B1
公开(公告)日：2003-09-02
申请号：US10092195
申请日：2002-03-06
申请人： Elyar E. Gasanov , Valery B. Kudryavtsev , Andrey A. Nikitin
发明人： Elyar E. Gasanov , Valery B. Kudryavtsev , Andrey A. Nikitin
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , G06F17/505
摘要： A method of determining a desired connection path between a pair of points of a net separated by one or more blockages, while reducing path delays and ramp time violations and without placing buffers within any of the blockages.
摘要翻译：一种确定由一个或多个阻塞分开的网络的一对点之间期望的连接路径的方法，同时减少路径延迟和斜坡时间违规，并且不在任何阻塞内放置缓冲器。

7. 发明授权

US07404166B2 Method and system for mapping netlist of integrated circuit to design 失效
标题翻译：将集成电路网表映射到设计的方法和系统
公开(公告)号：US07404166B2
公开(公告)日：2008-07-22
申请号：US11257289
申请日：2005-10-24
申请人： Alexander E. Andreev , Pavel Panteleev , Andrey A. Nikitin
发明人： Alexander E. Andreev , Pavel Panteleev , Andrey A. Nikitin
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/64
摘要： The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the netlist a cell in a template so that, for each cell of the netlist, its place in the template is as close as possible to its place obtained by the chaos algorithm. Simulating annealing optimization technique is applied to reduce a sum of wire length of the design.
摘要翻译：本发明提供了一种用于将集成电路的网表映射到设计的方法。该方法包括以下步骤。混沌算法用于从网表中为单元格设计获得最有利的位置。 Kuhn算法用于将网表中的每个单元格分配给模板中的单元，使得对于网表的每个单元，其在模板中的位置尽可能靠近其通过混沌算法获得的位置。应用模拟退火优化技术减少设计线长度的总和。

8. 发明授权

US07103868B2 Optimizing depths of circuits for Boolean functions 有权
标题翻译：优化布尔函数的电路深度
公开(公告)号：US07103868B2
公开(公告)日：2006-09-05
申请号：US10291982
申请日：2002-11-12
申请人： Andrey A. Nikitin , Alexander E. Andreev
发明人： Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Boolean circuits are designed with minimal depth by calculating the depth of an existing circuit. Those subtrees having a non-regular root cell (i.e., cells having other than one child or having a child of a type different from the cell) are balanced by constructing a new subtree. The cells are then iteratively transformed with parent and/or grandparent cells to reduce the depth of the circuit. The transformation may include balancing the subtree to make the parent cell the same type as the selected cell, or by creating a new cell as parent to the selected cell.
摘要翻译：通过计算现有电路的深度，布尔电路设计的最小深度。具有非正规根细胞（即，具有不同于一个子代的细胞或具有不同于细胞的子类的细胞）的子树通过构建新的子树来平衡。然后用母体和/或祖母细胞迭代转化细胞以减少电路的深度。转换可以包括平衡子树以使父单元与所选择的单元相同，或通过将新单元创建为所选单元格的父单元。

9. 发明授权

US06651239B1 Direct transformation of engineering change orders to synthesized IC chip designs 有权
标题翻译：将工程变更订单直接转换为合成IC芯片设计
公开(公告)号：US06651239B1
公开(公告)日：2003-11-18
申请号：US10008089
申请日：2001-11-13
申请人： Andrey A. Nikitin , Andrej A. Zolotykh , Nikola Radovanovic
发明人： Andrey A. Nikitin , Andrej A. Zolotykh , Nikola Radovanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A change, such as an ECO, is transformed to a gate-level netlist. The change is incorporated in cells of a synthesizable source design. A domain is defined in the netlist that contains cells that are equivalent to the cells of the source design that incorporate the change. The cells of the synthesizable source design that incorporate the change are substituted for the domain in the netlist. The substituted synthesizable source design domain is resynthesized into the gate-level netlist that includes the change.
摘要翻译：诸如ECO的变化被转换为门级网表。该变化被并入可合成的源设计的单元格中。在网表中定义了一个域，其中包含与包含该更改的源设计的单元格相同的单元格。合并该变更的可合成源设计的单元格代替网表中的域。替代的可合成源设计域被重新合并到包含该变化的门级网表中。

10. 发明授权

US08006209B2 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US08006209B2
公开(公告)日：2011-08-23
申请号：US12315998
申请日：2008-12-09
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。。。 xN，并输出命令和数据的顺序。

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