专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08832532B2 Dynamically controlling the number of local iterations in an iterative decoder 有权
标题翻译：动态地控制迭代解码器中的局部迭代次数
公开(公告)号：US08832532B2
公开(公告)日：2014-09-09
申请号：US13528237
申请日：2012-06-20
申请人： Anatoli A. Bolotov , Aleksey Alexandrovich Letunovskiy , Ivan Leonidovich Mazurenko , Lav D. Ivanovic , Fan Zhang
发明人： Anatoli A. Bolotov , Aleksey Alexandrovich Letunovskiy , Ivan Leonidovich Mazurenko , Lav D. Ivanovic , Fan Zhang
IPC分类号： H03M13/00
CPC分类号： H03M13/6325 , H03M13/1111 , H03M13/1128 , H03M13/2957
摘要： An iterative decoder dynamically controls the number of local iterations of error-correction decoding performed for each global iteration of channel detection. In so doing, the iterative decoder (i) limits the number of local iterations that are performed after error-correction decoding has likely encountered a trapping set and (ii) permits decoding to continue when error-correction decoding is on the path to converging on a valid codeword. To predict whether error-correction decoding is on the path to encountering a trapping set or converging on a valid codeword, a model is generated based on observed numbers of unsatisfied check nodes for a specified number of local iterations. For local iterations following the specified number of local iterations, the observed numbers of unsatisfied check nodes are then compared to the model to determine whether to continue or terminate local iterations of error-correction decoding.
摘要翻译：迭代解码器动态地控制针对信道检测的每个全局迭代执行的纠错解码的局部迭代次数。在这样做时，迭代解码器（i）限制纠错解码可能遇到陷阱集之后执行的局部迭代次数，并且（ii）当纠错解码在路径上收敛时允许解码继续一个有效的代码字。为了预测误差校正解码是否在遇到陷阱集合或收敛于有效码字的路径上，基于观察到的针对指定数量的本地迭代的不满足的校验节点的数量来生成模型。对于在指定数量的本地迭代之后的局部迭代，观察到的不满足校验节点的数量然后与模型进行比较，以确定是否继续或终止纠错解码的本地迭代。

2. 发明申请

US20130283114A1 Systems and Methods for Locating and Correcting Decoder Mis-Corrections 有权
标题翻译：用于定位和校正解码器误差校正的系统和方法
公开(公告)号：US20130283114A1
公开(公告)日：2013-10-24
申请号：US13450289
申请日：2012-04-18
申请人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
发明人： Shaohua Yang , Yang Han , Chung-Li Wang , Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav D. Ivanovic
IPC分类号： G06F11/07 , H03M13/05 , G06F11/10 , H03M13/09
CPC分类号： H03M13/00 , G11B20/1833 , G11B2020/1843 , G11B2020/185 , G11B2220/2516 , G11B2220/415 , H03M7/6005 , H03M13/093 , H03M13/1102 , H03M13/1108 , H03M13/1128 , H03M13/3723 , H03M13/3746 , H03M13/41 , H03M13/6511 , H03M13/6513
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括具有数据解码器电路，元件修改电路，元件修改日志和错误校正检测电路的数据解码电路的数据处理系统。

3. 发明申请

US20120324319A1 HIGH THROUGHPUT FRAME CHECK SEQUENCE MODULE ARCHITECTURE 有权
标题翻译：高通道帧检查序列模块架构
公开(公告)号：US20120324319A1
公开(公告)日：2012-12-20
申请号：US13161796
申请日：2011-06-16
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav Ivanovic
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav Ivanovic
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1004 , H03M13/091 , H03M13/616
摘要： Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.
摘要翻译：描述的实施例提供具有循环冗余校验（CRC）单元的帧校验序列（FCS）模块，其接收数据块（如果需要，填充到最大宽度）和第一状态向量，并且基于扩展CRC转换矩阵。 FCS模块还包括一组矩阵单元，每个矩阵单元被配置为将内部矢量乘以相应的校正矩阵，其中乘法产生一组乘积。复用器通过由最大字节数和原始宽度确定的控制信号选择来自该组乘积的第二状态向量。

4. 发明申请

US20120076298A1 UNIFIED ARCHITECTURE FOR CRYPTO FUNCTIONAL UNITS 有权
标题翻译：统一的结构功能单位
公开(公告)号：US20120076298A1
公开(公告)日：2012-03-29
申请号：US12892455
申请日：2010-09-28
申请人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Igor Kucherenko , Alexei Galatenko
发明人： Anatoli A. Bolotov , Mikhail I. Grinchuk , Lav Ivanovic , Igor Kucherenko , Alexei Galatenko
IPC分类号： H04K1/00
CPC分类号： H04L9/0643 , H04L9/0631 , H04L2209/125
摘要： In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks.
摘要翻译：在所描述的实施例中，统一的加密功能单元（CFU）块架构为高级通信处理器提供了在高速硬件内提供并行和并发处理多个加密操作/事务的能力，以支持不同的安全标准（例如，从IPsec，3GPP）。特别地，统一CFU块架构的每个CFU块包括基于FIFO的接口，交换机和封装的加密/哈希器。统一的CFU块架构允许在具有加密功能块的ASIC设计中的密码块的插入式解决方案。

5. 发明授权

US07856577B2 Command language for memory testing 有权
标题翻译：内存测试的命令语言
公开(公告)号：US07856577B2
公开(公告)日：2010-12-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F11/00
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

6. 发明申请

US20090316507A1 Generation Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories 有权
标题翻译：在多个记忆的内存自检过程中产生测试序列
公开(公告)号：US20090316507A1
公开(公告)日：2009-12-24
申请号：US12142912
申请日：2008-06-20
申请人： Alexandre E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexandre E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/16 , G11C2029/0401 , G11C2029/2602
摘要： The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal.
摘要翻译：本发明涉及一种包括模块化存储器和地址定位器电路的装置。模块化存储器可以被配置为响应于第一端口地址信号，第二端口地址信号，初始状态参数，目标状态参数，等等，产生当前地址信号，第一数据输出信号和第二数据输出信号第一端口使能信号，第二端口使能信号，写使能信号，数据输入信号，第一位置信号和第二位置信号。地址定位器电路可以被配置为响应于第一端口地址信号，第二端口地址信号和当前地址信号而产生第一位置信号和第二位置信号。

7. 发明授权

US07231383B2 Search engine for large-width data 有权
标题翻译：大型数据搜索引擎
公开(公告)号：US07231383B2
公开(公告)日：2007-06-12
申请号：US10137874
申请日：2002-05-01
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F17/30 , G06F15/16
CPC分类号： G06F9/342 , Y10S707/99931 , Y10S707/99933 , Y10S707/99934
摘要： A search engine architecture substitutes short indices for large data widths, thereby reducing widths required for input to and output from the search engine. The search engine system comprises a search engine responsive to an input address to access an index in the search engine. The index has a width no greater than logarithm on base 2 of the search engine capacity, thereby permitting the search engine to be embodied in an IC chip of reduced area. A driver responds to input commands and to the search engine status to manage indices in the search engine and enable the memory to access its addressable locations based on indices in the search engine.
摘要翻译：搜索引擎架构将短索引替换为大数据宽度，从而减少输入到搜索引擎输出所需的宽度。搜索引擎系统包括响应于输入地址以访问搜索引擎中的索引的搜索引擎。该索引具有不大于搜索引擎容量的基础2上的对数的宽度，从而允许搜索引擎体现在缩小区域的IC芯片中。驱动程序响应输入命令和搜索引擎状态来管理搜索引擎中的索引，并使内存能够基于搜索引擎中的索引访问其可寻址位置。

8. 发明授权

US06662287B1 Fast free memory address controller 失效
标题翻译：快速可用内存地址控制器
公开(公告)号：US06662287B1
公开(公告)日：2003-12-09
申请号：US10000243
申请日：2001-10-18
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F1200
CPC分类号： G06F12/023 , Y10S707/99953 , Y10S707/99956
摘要： A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.
摘要翻译：用于管理存储器中的地址分配的存储器管理器被构造为具有顶部顶点，底部水平和至少一个中间水平的分层树。底层包含多个底部顶点，每个底部顶点包含多个存储器中相应地址的自由或取代状态的表示。每个中间体包含至少一个包含多个标签的层次顶点，使得每个标签与子顶点相关联，并且定义包含相应子顶点的路径是否包含在包含至少一个自由表示的相应底层顶点中。一个分配命令将第一个自由地址的表示更改为Taken，一个free命令将指定地址的表示更改为Free。更改层次顶点中的标签以反映底层顶点的路径条件。

9. 发明授权

US08898539B2 Correcting errors in miscorrected codewords using list decoding 有权
标题翻译：使用列表解码校正错误码字中的错误
公开(公告)号：US08898539B2
公开(公告)日：2014-11-25
申请号：US13611158
申请日：2012-09-12
申请人： Yang Han , Shaohua Yang , Zongwang Li , Fan Zhang , Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
发明人： Yang Han , Shaohua Yang , Zongwang Li , Fan Zhang , Anatoli A. Bolotov , Mikhail I. Grinchuk , Paul G. Filseth , Lav D. Ivanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/6337 , H03M13/09 , H03M13/1102 , H03M13/1128 , H03M13/152 , H03M13/2957 , H03M13/3707 , H03M13/3753 , H03M13/451
摘要： A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.
摘要翻译：通信系统的接收路径包括纠错解码器，错误检测解码器和码字调节器。误差校正解码器对接收的码字进行纠错解码，以生成有效的码字。错误检测解码器对有效码字执行错误检测解码，以确定有效码字是否是发送的正确码字。如果有效码字不是正确的码字，则码字调节器通过向有效码字应用误差向量来生成经调整的有效码字。错误检测解码器对经调整的有效码字执行错误检测解码，以确定调整后的有效码字是否为正确码字。当纠错解码器产生不正确的有效码字时，调整有效码字使得接收路径能够恢复正确的码字而不重传或重新检测码字。

10. 发明授权

US08683291B2 High throughput frame check sequence module architecture 有权
标题翻译：高吞吐量帧校验序列模块架构
公开(公告)号：US08683291B2
公开(公告)日：2014-03-25
申请号：US13161796
申请日：2011-06-16
申请人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav Ivanovic
发明人： Mikhail I. Grinchuk , Anatoli A. Bolotov , Lav Ivanovic
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1004 , H03M13/091 , H03M13/616
摘要： Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.
摘要翻译：描述的实施例提供具有循环冗余校验（CRC）单元的帧校验序列（FCS）模块，其接收数据块（如果需要，填充到最大宽度）和第一状态向量，并且基于扩展CRC转换矩阵。 FCS模块还包括一组矩阵单元，每个矩阵单元被配置为将内部矢量乘以相应的校正矩阵，其中乘法产生一组乘积。复用器通过由最大字节数和原始宽度确定的控制信号选择来自该组乘积的第二状态向量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式