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1. 发明授权

US08095845B1 System and method for assigning code blocks to constituent decoder units in a turbo decoding system having parallel decoding units 有权
标题翻译：用于在具有并行解码单元的turbo解码系统中向组成解码器单元分配代码块的系统和方法
公开(公告)号：US08095845B1
公开(公告)日：2012-01-10
申请号：US12169703
申请日：2008-07-09
申请人： Alexander E. Andreev , Sergey Y. Gribok , Vojislav Vukovic
发明人： Alexander E. Andreev , Sergey Y. Gribok , Vojislav Vukovic
IPC分类号： H03M13/00
CPC分类号： H03M13/6561 , H03M13/2957
摘要： A system for, and method of, assigning code blocks to constituent decoding units in a turbo decoding system having parallel decoding units. In one embodiment, the system includes: (1) a resource model generator configured to generate a model that represents the constituent decoding units and memories thereof along two dimensions, (2) a decoding unit number calculator associated with the resource model generator and configured to determine, for each of the code blocks, a number of the constituent decoding units to use to decode subblocks of each of the code blocks, (3) a rectangle mapper associated with the decoding unit number calculator and configured to generate a mapping in which the code blocks are mapped to the model and (4) a code block assigner associated with the rectangle mapper and configured to assign the subblocks of each code block to the constituent decoding units in accordance with the mapping.
摘要翻译：一种用于在具有并行解码单元的turbo解码系统中将代码块分配给组成解码单元的系统和方法。在一个实施例中，系统包括：（1）资源模型生成器，被配置为沿着二维生成表示组成解码单元及其存储器的模型，（2）与资源模型生成器相关联的解码单元数计算器，为每个代码块确定用于解码每个代码块的子块的多个组成解码单元，（3）与解码单元数计算器相关联的被配置为生成映射的映射，其中，代码块被映射到模型，（4）与矩形映射器相关联的代码块分配器，并且被配置为根据映射将每个代码块的子块分配给组成解码单元。

2. 发明授权

US07856577B2 Command language for memory testing 有权
标题翻译：内存测试的命令语言
公开(公告)号：US07856577B2
公开(公告)日：2010-12-21
申请号：US11944104
申请日：2007-11-21
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F11/00
CPC分类号： G06F11/27 , G06F8/41 , G11C29/16
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译：提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。

3. 发明授权

US07404166B2 Method and system for mapping netlist of integrated circuit to design 失效
标题翻译：将集成电路网表映射到设计的方法和系统
公开(公告)号：US07404166B2
公开(公告)日：2008-07-22
申请号：US11257289
申请日：2005-10-24
申请人： Alexander E. Andreev , Pavel Panteleev , Andrey A. Nikitin
发明人： Alexander E. Andreev , Pavel Panteleev , Andrey A. Nikitin
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/64
摘要： The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized to assign each cell of the netlist a cell in a template so that, for each cell of the netlist, its place in the template is as close as possible to its place obtained by the chaos algorithm. Simulating annealing optimization technique is applied to reduce a sum of wire length of the design.
摘要翻译：本发明提供了一种用于将集成电路的网表映射到设计的方法。该方法包括以下步骤。混沌算法用于从网表中为单元格设计获得最有利的位置。 Kuhn算法用于将网表中的每个单元格分配给模板中的单元，使得对于网表的每个单元，其在模板中的位置尽可能靠近其通过混沌算法获得的位置。应用模拟退火优化技术减少设计线长度的总和。

4. 发明授权

US07231383B2 Search engine for large-width data 有权
标题翻译：大型数据搜索引擎
公开(公告)号：US07231383B2
公开(公告)日：2007-06-12
申请号：US10137874
申请日：2002-05-01
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F17/30 , G06F15/16
CPC分类号： G06F9/342 , Y10S707/99931 , Y10S707/99933 , Y10S707/99934
摘要： A search engine architecture substitutes short indices for large data widths, thereby reducing widths required for input to and output from the search engine. The search engine system comprises a search engine responsive to an input address to access an index in the search engine. The index has a width no greater than logarithm on base 2 of the search engine capacity, thereby permitting the search engine to be embodied in an IC chip of reduced area. A driver responds to input commands and to the search engine status to manage indices in the search engine and enable the memory to access its addressable locations based on indices in the search engine.
摘要翻译：搜索引擎架构将短索引替换为大数据宽度，从而减少输入到搜索引擎输出所需的宽度。搜索引擎系统包括响应于输入地址以访问搜索引擎中的索引的搜索引擎。该索引具有不大于搜索引擎容量的基础2上的对数的宽度，从而允许搜索引擎体现在缩小区域的IC芯片中。驱动程序响应输入命令和搜索引擎状态来管理搜索引擎中的索引，并使内存能够基于搜索引擎中的索引访问其可寻址位置。

5. 发明授权

US07103868B2 Optimizing depths of circuits for Boolean functions 有权
标题翻译：优化布尔函数的电路深度
公开(公告)号：US07103868B2
公开(公告)日：2006-09-05
申请号：US10291982
申请日：2002-11-12
申请人： Andrey A. Nikitin , Alexander E. Andreev
发明人： Andrey A. Nikitin , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Boolean circuits are designed with minimal depth by calculating the depth of an existing circuit. Those subtrees having a non-regular root cell (i.e., cells having other than one child or having a child of a type different from the cell) are balanced by constructing a new subtree. The cells are then iteratively transformed with parent and/or grandparent cells to reduce the depth of the circuit. The transformation may include balancing the subtree to make the parent cell the same type as the selected cell, or by creating a new cell as parent to the selected cell.
摘要翻译：通过计算现有电路的深度，布尔电路设计的最小深度。具有非正规根细胞（即，具有不同于一个子代的细胞或具有不同于细胞的子类的细胞）的子树通过构建新的子树来平衡。然后用母体和/或祖母细胞迭代转化细胞以减少电路的深度。转换可以包括平衡子树以使父单元与所选择的单元相同，或通过将新单元创建为所选单元格的父单元。

6. 发明授权

US07050582B1 Pseudo-random one-to-one circuit synthesis 有权
标题翻译：伪随机一对一电路合成
公开(公告)号：US07050582B1
公开(公告)日：2006-05-23
申请号：US09883733
申请日：2001-06-18
申请人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
发明人： Alexander E. Andreev , Igor A. Vikhliantsev , Ranko Scepanovic
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L9/0668
摘要： A method of defining a transformation between an input signal and an output signal. The transformation may implement a pseudo-random one-to-one function that may be implemented in hardware and/or software or modeled in software. The method may comprise the steps of (A) allocating the input signal among a plurality of block input signals, (B) establishing a plurality of transfer functions where each transfer function may be configured to present a plurality of unique symbols as a block output signal responsive to said block input signal, and (C) concatenating the block output signals to form the output signal.
摘要翻译：一种定义输入信号和输出信号之间变换的方法。该转换可以实现可以在硬件和/或软件中实现或以软件建模的伪随机一对一功能。该方法可以包括以下步骤：（A）在多个块输入信号之间分配输入信号，（B）建立多个传递函数，其中每个传递函数可被配置为呈现多个唯一符号作为块输出信号响应于所述块输入信号，以及（C）串联块输出信号以形成输出信号。

7. 发明授权

US06988252B2 Universal gates for ICs and transformation of netlists for their implementation 失效
标题翻译： IC的通用门户，以及网路数据库的实施转型
公开(公告)号：US06988252B2
公开(公告)日：2006-01-17
申请号：US10633856
申请日：2003-08-04
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： An original netlist is transformed to one employing universal gates. A negation net is created for each net coupled to an input or output of each gate and an input of each inverter in the original net. Each gate is removed from the original netlist and a universal gate is inserted so that the nets previously coupled to the inputs and output of the removed gate and a negation of those nets are coupled to the inputs and outputs of the inserted universal gate in a selected arrangement. Each inverter is removed from the original netlist and the net previously coupled to the input of the inverter is negated. A universal gate comprises gates performing anding and oring functions whose inputs and outputs are selectively coupled to the nets of the original netlist, and their negations.
摘要翻译：一个原始网表被转换为一个采用通用门。针对耦合到每个门的输入或输出的每个网络以及原始网络中每个逆变器的输入产生一个否定网。每个门从原始网表移除，并且插入通用门，使得先前耦合到去除的门的输入和输出的网络以及这些网络的否定被耦合到所选择的插入的通用门的输入和输出安排。每个逆变器从原始网表中移除，并且先前耦合到逆变器输入端的网络被否定。通用门包括执行输入和输出功能的门，其输入和输出选择性地耦合到原始网表的网络，以及它们的否定。

8. 发明授权

US06941314B2 User selectable editing protocol for fast flexible search engine 有权
标题翻译：用户可选择的编辑协议，用于快速灵活的搜索引擎
公开(公告)号：US06941314B2
公开(公告)日：2005-09-06
申请号：US10123295
申请日：2002-04-15
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F17/30327 , Y10S707/99937 , Y10S707/99942 , Y10S707/99943
摘要： A method of editing a sorted tree data structure includes selecting a minimum number of entries and a maximum number of entries in each vertex of the sorted tree data structure. If inserting an entry into a bottom vertex of the sorted tree data structure exceeds the maximum number of entries in the bottom vertex, then the entries are redistributed in the sorted tree data structure or a new bottom vertex is created so that no bottom vertex has more than the maximum number of entries and no fewer than the minimum number of entries. If deleting an entry from the bottom vertex results in fewer than the minimum number of entries, then the entries are redistributed in the sorted tree data structure or the bottom vertex is deleted so that no bottom vertex has fewer than the minimum number of entries and no bottom vertex has more than the maximum number of entries.
摘要翻译：编辑排序树数据结构的方法包括：选择排序树数据结构的每个顶点中的条目的最小数目和最大数目的条目。如果将条目插入到排序树数据结构的底部顶点超过底部顶点中的最大条目数，则条目将在排序的树数据结构中重新分布，或者创建一个新的底部顶点，以便底部顶点不再有比最大条目数不少于最小条目数。如果从底部顶点删除条目导致少于最小条目数，则条目将在排序的树数据结构中重新分配，或者删除底部顶点，以便没有底部顶点少于最小条目数，并且没有底部顶点具有多于最大条目数。

9. 发明授权

US06662287B1 Fast free memory address controller 失效
标题翻译：快速可用内存地址控制器
公开(公告)号：US06662287B1
公开(公告)日：2003-12-09
申请号：US10000243
申请日：2001-10-18
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： G06F1200
CPC分类号： G06F12/023 , Y10S707/99953 , Y10S707/99956
摘要： A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.
摘要翻译：用于管理存储器中的地址分配的存储器管理器被构造为具有顶部顶点，底部水平和至少一个中间水平的分层树。底层包含多个底部顶点，每个底部顶点包含多个存储器中相应地址的自由或取代状态的表示。每个中间体包含至少一个包含多个标签的层次顶点，使得每个标签与子顶点相关联，并且定义包含相应子顶点的路径是否包含在包含至少一个自由表示的相应底层顶点中。一个分配命令将第一个自由地址的表示更改为Taken，一个free命令将指定地址的表示更改为Free。更改层次顶点中的标签以反映底层顶点的路径条件。

10. 发明授权

US06324674B2 Method and apparatus for parallel simultaneous global and detail routing 失效
标题翻译：并行同时全局和细节路由的方法和装置
公开(公告)号：US06324674B2
公开(公告)日：2001-11-27
申请号：US09062309
申请日：1998-04-17
申请人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
发明人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.
摘要翻译：一种用于在集成电路设计中布线网络的方法，所述方法包括以下步骤：将集成电路设计与沿第一方向和第二方向的线分开，形成具有顶点和边缘的路由图，其中顶点对应于第一方向上的线在第二方向上交叉线，将并行网络作为所述路由图的函数，并行处理器基本上同时运行，确定集成电路设计中的不同区域之间的相对电线拥塞，以及重新路由通过区域的网络电线拥塞比较高

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