会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明申请
    • Coder and a Method of Coding For Codes With a Parity-Complementary Word Assignment Having a Constraint of D1=,R=2
    • 编码器和编码代码的方法,其中具有约束D1 =,R = 2的奇偶互补字分配
    • US20090015446A1
    • 2009-01-15
    • US12097570
    • 2006-12-08
    • Willem Marie Julia Marcel CoeneAndries Pieter HekstraHiroyuki YamagishiMakoto Noda
    • Willem Marie Julia Marcel CoeneAndries Pieter HekstraHiroyuki YamagishiMakoto Noda
    • H03M7/00
    • G11B20/1426G11B20/10055G11B20/10296G11B2020/1453G11B2020/1457H03M5/145H03M7/40H03M13/29H03M13/31H03M13/3761H03M13/3972H03M13/41
    • Presently known d=1 codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index Tmax+1 t. In the code according to the invention the overall code has the property that the respective channel bit sequences that are encoded from the same message-bit sequence, starting from any possible state of the finite-state-machine, for each of the two values of a DC-control bit, that is part of a given user word have opposite parities for the sequences generated from the starting state up to the state where both encoder paths merge. For the case that the encoder paths do not merge, there is no such constraint. Finally, a new d=1, k=10 sliding-block decodable RLL code is disclosed with the following properties: (i) it has an r=2 constraint which is the lowest MTR value that is compatible with a rate R=⅔; (ii) it enables practical SISO-RLL decoding because of its compact 2-to-3 mapping; and (iii) the new code uses a parity-complementary word assignment4 (PCWA) for DC-control.
    • 目前已知的d = 1代码具有由连续的2T运行组成的长列,并且总体出现最短的2T运行的频率,从而降低位检测器的性能通过使用MTR约束为2的代码,改进了位检测 已完成。 提出了一种以系统方式构建的代码,其提供MTR约束为2的代码。 公开了这样的代码的变型,其中使用一个子代码,其中编码状态被分为编码类别以及代码字被分成代码字类型。 然后,对于给定子码,如果所述下一子码的所述后续码字属于编码类的编码状态之一,则可以将类型t的码字与下一子码的码字连接, 指数Tmax + 1t。 在根据本发明的代码中,总代码具有以下特性:从相同消息比特序列编码的各个信道比特序列,从有限状态机的任何可能状态开始,对于两个值的 作为给定用户字的一部分的DC控制位对于从起始状态直到两个编码器路径合并的状态产生的序列具有相反的奇偶校验。 对于编码器路径不合并的情况,没有这样的限制。 最后,公开了一种新的d = 1,k = 10滑块可解码的RLL码,具有以下特性:(i)它具有r = 2约束,其是与速率R = 2 / 3; (ii)由于其紧凑的2对3映射,它使实用的SISO-RLL解码成为可能; 和(iii)新的代码使用奇偶互补字分配4(PCWA)进行DC控制。
    • 6. 发明授权
    • Authentication system wherein definition signals of two devices are
altered, communicated between the two devices, and compared
    • 验证系统,其中两个设备的定义信号被改变,在两个设备之间进行通信并进行比较
    • US6042006A
    • 2000-03-28
    • US915015
    • 1997-08-20
    • Johan Van TilburgAndries Pieter Hekstra
    • Johan Van TilburgAndries Pieter Hekstra
    • G07F7/10H04L9/00G06K5/00
    • G07F7/1008G06Q20/341G06Q20/4012G06Q20/40975
    • An authentication system having a first device and a second device between which signals may be communicated. The first device includes a first memory for storing a definition signal and the first device generates a first signal to be communicated to the second device. The first device also generates a first alteration signal, and introduces an alteration into a first section of the definition signal stored in the first memory in accordance with the first alteration signal. The second device includes a second memory for storing the definition signal, and generates, in response to a receipt of the first signal, a second signal to be communicated to the first device. The second signal includes a second section of the definition signal stored in the second memory, and the second device also generates a second alteration signal and introduces an alteration into a third section of the definition signal stored in the second memory in accordance with the second alteration signal. In addition, the first device compares the second section of the definition signal in the second signal originating from the second device with a corresponding section of the definition signal stored in the first memory, and introduces the alteration into the first section of the definition signal stored in the first memory in accordance with a comparison result. The first and third sections, moreover, are corresponding sections of the definition signals stored in the first and second memories, respectively.
    • 一种具有第一设备和第二设备的认证系统,在该设备之间可以传送信号。 第一设备包括用于存储定义信号的第一存储器,并且第一设备生成要传送到第二设备的第一信号。 第一设备还产生第一改变信号,并且根据第一改变信号将改变引入存储在第一存储器中的定义信号的第一部分。 第二装置包括用于存储定义信号的第二存储器,并且响应于第一信号的接收而产生要传送到第一装置的第二信号。 第二信号包括存储在第二存储器中的定义信号的第二部分,并且第二装置还产生第二改变信号,并根据第二变更将改变引入存储在第二存储器中的定义信号的第三部分 信号。 此外,第一装置将来自第二装置的第二信号中的定义信号的第二部分与存储在第一存储器中的定义信号的相应部分进行比较,并将该改变引入存储的定义信号的第一部分 在第一个内存中按照比较结果。 此外,第一和第三部分分别是存储在第一和第二存储器中的定义信号的相应部分。
    • 10. 发明申请
    • SISO DECODER WITH SUB-BLOCK PROCESSING AND SUB-BLOCK BASED STOPPING CRITERION
    • 具有子块加工和基于子块的停止标准的SISO解码器
    • US20090019332A1
    • 2009-01-15
    • US10596543
    • 2004-12-08
    • Andries Pieter HekstraJohannus Theodorus Dielissen
    • Andries Pieter HekstraJohannus Theodorus Dielissen
    • H03M13/05G06F11/10
    • H03M13/3905H03M13/2975H03M13/3972
    • The present invention relates to SISO decoder for iteratively decoding a block of received information symbols (r), in particular for use in a turbo decoder, said block being divided into a number of windows of information symbols. In order to achieve a significant reduction of power consumption a SISO decoder is proposed comprising: at least one SISO decoding unit (17, 21) for SISO decoding of the received information symbols (r) of a window, a window activity flag storage (23) for storing window activity flags indicating if a window is made active or inactive, a window activity flag setting unit (17) for setting said window activity flag active or inactive, wherein said window activity flags are initially set active and wherein a window activity flag of a window is set inactive if a certitude indication value of the information symbols in said window are above a predetermined certitude threshold, a window activity flag reading unit (17, 22) for reading said window activity flags from said window activity flag storage (23), and a control unit (27) for controlling said at least one SISO decoding unit (17) based on the read window activity flags such that the information symbols of a window for which the corresponding window activity flag is set inactive are not SISO decoded in subsequent iterations.
    • 本发明涉及用于对接收的信息符号(r)的块进行迭代解码的SISO解码器,特别是在turbo解码器中使用,所述块被划分成多个信息符号窗口。 为了实现功耗的显着降低,提出了一种SISO解码器,其包括:至少一个SISO解码单元(17,21),用于SISO解码窗口的接收信息符号(r),窗口活动标志存储器(23 ),用于存储指示窗口是活动还是非活动的窗口活动标志;窗口活动标志设置单元(17),用于设置所述窗口活动标志为活动或非活动,其中所述窗口活动标志初始设置为有效,并且其中窗口活动标志 如果所述窗口中的信息符号的认证指示值高于预定认证阈值,则窗口的窗口活动标志读取单元(17,22)用于从所述窗口活动标志存储器(23)读取所述窗口活动标志 )和控制单元(27),用于基于所读取的窗口活动标志来控制所述至少一个SISO解码单元(17),使得所述对应的窗口的信息符号 ding窗口活动标志置为无效SISO在后续迭代中解码。