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1. 发明授权

US08551858B2 Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory 有权
标题翻译：自对准SI丰富的氮化物电荷陷阱层隔离电荷陷阱闪存
公开(公告)号：US08551858B2
公开(公告)日：2013-10-08
申请号：US12699635
申请日：2010-02-03
申请人： Shenqing Fang , Angela Hui , Shao-Yu Ting , Inkuk Kang , Gang Xue
发明人： Shenqing Fang , Angela Hui , Shao-Yu Ting , Inkuk Kang , Gang Xue
IPC分类号： H01L21/76
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/76224 , H01L27/11568
摘要： A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance. U-shaped trap layer edges allow for increased packing density and integration while maintaining isolation between trap layers.
摘要翻译：公开了一种在圆形有源区域角上制造具有U形陷阱层的存储器件的方法。在本发明中，在形成电荷俘获层之前进行STI工艺。在STI处理之后，活动区域的尖角暴露，使其可用于四舍五入。四舍五入改善了存储设备的性能特征。在舍入处理之后，形成底部氧化物层，氮化物层和牺牲顶部氧化物层。施加到电荷捕获层的有机底部抗反射涂层被平坦化。现在蚀刻有机底部抗反射涂层，牺牲顶部氧化物层和氮化物层，而不在有源区域上蚀刻牺牲顶部氧化物层和氮化物层。在蚀刻之后，电荷捕获层具有横截面的U形外观。 U形陷阱层边缘允许增加堆积密度和集成度，同时保持捕集层之间的隔离。

2. 发明授权

US08384146B2 Methods for forming a memory cell having a top oxide spacer 有权
标题翻译：形成具有顶部氧化物间隔物的存储单元的方法
公开(公告)号：US08384146B2
公开(公告)日：2013-02-26
申请号：US13428848
申请日：2012-03-23
申请人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
发明人： Shenqing Fang , Angela Hui , Gang Xue , Alexander Nickel , Kashmir Sahota , Scott Bell , Chun Chen , Wai Lo
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/792
摘要： Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.
摘要翻译：公开了制造具有间隔层的半导体存储单元的方法。一种方法包括在衬底中形成多个源极/漏极区域，其中多个源极/漏极区域形成在沟槽之间，在多个源极/漏极区域上方和沟槽中形成第一氧化物层，形成电荷存储层在电荷存储层的分离部分之间，在形成空间的沟槽中分离电荷存储层。该方法还包括形成间隔层以填充电荷存储层的分离部分之间的空间并在空间上方上升预定距离。在电荷存储层和间隔层上方形成第二氧化物层，并且在第二氧化物层上方形成多晶硅层。

3. 发明授权

US08035153B2 Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜和蚀刻用于闪存和其他半导体应用的自对准图案化方法
公开(公告)号：US08035153B2
公开(公告)日：2011-10-11
申请号：US12788177
申请日：2010-05-26
申请人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
发明人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/11568
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。然后在核心单元之间完全或部分蚀刻捕获层。去除非保形膜。并形成顶部氧化物。如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

4. 发明授权

US07906807B2 Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics 有权
标题翻译：在闪速存储器单元的位线结中使用聚合物间隔物和Si沟槽以改善TPD特性
公开(公告)号：US07906807B2
公开(公告)日：2011-03-15
申请号：US12827069
申请日：2010-06-30
申请人： Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , Kuo-Tung Chang , Huaqiang Wu
发明人： Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , Kuo-Tung Chang , Huaqiang Wu
IPC分类号： H01L29/92 , H01L29/76 , H01L21/336
CPC分类号： H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。位线电介质可以延伸到半导体中。存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

5. 发明申请

US20100264480A1 USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS 有权
标题翻译：在闪速存储器单元的位线结中使用聚合物间隔物和硅酸盐以提高TPD特性
公开(公告)号：US20100264480A1
公开(公告)日：2010-10-21
申请号：US12827069
申请日：2010-06-30
申请人： Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , K.T Chang , Huaqiang Wu
发明人： Ning Cheng , Calvin Gabriel , Angela Hui , Lei Xue , Harpreet Kaur Sachar , Phillip Lawrence Jones , Hiro Kinoshita , K.T Chang , Huaqiang Wu
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/7923
摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.
摘要翻译：提供了具有改善的TPD特性的存储器件和制造存储器件的方法。存储器件在半导体衬底上包含两个或更多存储器单元，并且在存储器单元之间包含位线电介质。位线电介质可以延伸到半导体中。存储单元包含一个或多个电荷存储节点，第一多晶硅栅极，一对第一位线和一对第二位线。与第一位线的能级和掺杂剂的浓度相比，第二位线可以形成在更高的能级，更高浓度的掺杂剂或其组合。

6. 发明申请

US20100099249A1 SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK 有权
标题翻译：选择性硅胶形成使用耐蚀蚀回填
公开(公告)号：US20100099249A1
公开(公告)日：2010-04-22
申请号：US12644457
申请日：2009-12-22
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/285 , H01L21/3205
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

7. 发明授权

US07696038B1 Methods for fabricating flash memory devices 有权
标题翻译：制造闪存设备的方法
公开(公告)号：US07696038B1
公开(公告)日：2010-04-13
申请号：US11412365
申请日：2006-04-26
申请人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Timothy Thurgate , Wei Zheng , Ashot Melik-Martirosian , Angela Hui , Chih-Yuh Yang
发明人： Ning Cheng , Kuo-Tung Chang , Hiroyuki Kinoshita , Timothy Thurgate , Wei Zheng , Ashot Melik-Martirosian , Angela Hui , Chih-Yuh Yang
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , G11C16/3418 , G11C16/3427
摘要： Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.
摘要翻译：提供了制造闪速存储器件的方法。根据本发明的示例性实施例，一种用于制造存储器件的方法包括形成覆盖衬底的第一栅极堆叠和第二栅极堆叠。在第一栅极堆叠和第二栅极堆叠之间的沟槽被蚀刻到衬底中。第一杂质掺杂区域形成在沟槽下面的衬底内。

8. 发明授权

US07691751B2 Selective silicide formation using resist etchback 有权
标题翻译：使用抗蚀剂回蚀的选择性硅化物形成
公开(公告)号：US07691751B2
公开(公告)日：2010-04-06
申请号：US11924823
申请日：2007-10-26
申请人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
发明人： Kyunghoon Min , Angela Hui , Hiroyuki Kinoshita , Ning Cheng , Mark Chang
IPC分类号： H01L21/4763
CPC分类号： H01L27/115 , H01L21/28518 , H01L21/31144 , H01L27/105 , H01L27/1052 , H01L27/11534 , H01L27/11568 , H01L29/665
摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.
摘要翻译：提供了在存储器件上选择性地形成金属硅化物的方法。所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

9. 发明申请

US20070026675A1 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US20070026675A1
公开(公告)日：2007-02-01
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

10. 发明授权

US07023046B2 Undoped oxide liner/BPSG for improved data retention 有权
标题翻译：未掺杂氧化物衬垫/ BPSG，以改善数据保留
公开(公告)号：US07023046B2
公开(公告)日：2006-04-04
申请号：US10617450
申请日：2003-07-11
申请人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
发明人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31612 , H01L21/31625 , H01L27/115 , H01L29/511
摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.
摘要翻译：具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在相同的沉积室。

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