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1. 发明申请

US20170041099A1 Multiuse Data Channel 审中-公开
标题翻译：多用数据通道
公开(公告)号：US20170041099A1
公开(公告)日：2017-02-09
申请号：US14820137
申请日：2015-08-06
申请人： Ara Patapoutian , Hieu V. Nguyen
发明人： Ara Patapoutian , Hieu V. Nguyen
IPC分类号： H04L1/00 , H03M13/11 , G11C29/52 , H03M13/29 , G06F11/10
CPC分类号： H04L1/0045 , G06F11/1072 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/2906 , H03M13/6516 , H03M13/6561
摘要： Presented is a data channel with selectable components, such as encoders or decoders. Also, data having different data signal characteristics can be processed through a data channel based on the data signal characteristics. Further, a data channel may have independent encoding path and an independent decoding path. For example, a first data transmission having first data signal characteristics may be processed via a data channel based on a first selected set of components of the data channel and a second data transmission having second data signal characteristics different than the first data signal characteristics may be processed via the data channel using a second selected set of components in the data channel. The first selected set of components may be different than the second selected set of components, but may share one or more common components.
摘要翻译：提出了具有可选组件的数据通道，例如编码器或解码器。此外，可以基于数据信号特性通过数据信道来处理具有不同数据信号特性的数据。此外，数据信道可以具有独立的编码路径和独立的解码路径。例如，具有第一数据信号特性的第一数据传输可以经由数据信道基于数据信道的第一选定组件集合进行处理，并且具有与第一数据信号特性不同的第二数据信号特性的第二数据传输可以是通过数据信道使用数据信道中的第二组选择的组来处理。第一选择的组件集合可以不同于第二选择的组件集合，但是可以共享一个或多个公共组件。

2. 发明授权

US09473266B1 Scheduling strategies for iterative decoders 有权
标题翻译：迭代解码器的调度策略
公开(公告)号：US09473266B1
公开(公告)日：2016-10-18
申请号：US12473728
申请日：2009-05-28
申请人： Ara Patapoutian , Bruce Buch , Rose Shao
发明人： Ara Patapoutian , Bruce Buch , Rose Shao
IPC分类号： G06F11/00 , H04L1/00
CPC分类号： H03M13/1111 , H03M13/1105 , H03M13/3738 , H03M13/3746 , H03M13/3784 , H03M13/616 , H03M13/6325 , H04L1/0057
摘要： An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.
摘要翻译：控制迭代解码器以通过对该块执行一个或多个解码迭代来迭代地解码块。迭代解码器使用奇偶校验矩阵，并且可以被配置为处理用于并行，顺序或并行和顺序（“混合”）奇偶校验约束更新的组合的奇偶校验矩阵。

3. 发明授权

US08760986B2 Read channel throughput management 有权
标题翻译：读取通道吞吐量管理
公开(公告)号：US08760986B2
公开(公告)日：2014-06-24
申请号：US13408849
申请日：2012-02-29
申请人： Prafulla Bollampalli Reddy , Hui Su , Michelle Elaine Blankenship , Eddie Wai Pun , John Marc Wright , Ara Patapoutian , Hieu V Nguyen
发明人： Prafulla Bollampalli Reddy , Hui Su , Michelle Elaine Blankenship , Eddie Wai Pun , John Marc Wright , Ara Patapoutian , Hieu V Nguyen
IPC分类号： G11B11/00
CPC分类号： G11B20/1217 , G11B5/09 , G11B20/10527 , G11B20/1833 , G11B2020/10759 , G11B2020/10916 , G11B2020/1232 , G11B2020/1295 , G11B2020/185
摘要： An implementation of a system disclosed herein provides a method of deferring decoding of a data sector received at a read channel of a storage device, in response to determining that a data sector cannot be decoded by a first decoder and storing the data sector for further processing by a second decoder.
摘要翻译：响应于确定数据扇区不能由第一解码器解码并存储数据扇区用于进一步处理的方法，本文公开的系统的实现提供了一种在存储设备的读取信道上推迟对数据扇区进行解码的方法通过第二解码器。

4. 发明授权

US08627175B2 Opportunistic decoding in memory systems 有权
标题翻译：内存系统中的机会解码
公开(公告)号：US08627175B2
公开(公告)日：2014-01-07
申请号：US12891490
申请日：2010-09-27
申请人： Ara Patapoutian , Bernardo Rub , Bruce D. Buch
发明人： Ara Patapoutian , Bernardo Rub , Bruce D. Buch
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1048 , G11C16/26 , G11C29/844 , H03M13/1108 , H03M13/1111 , H03M13/3707 , H03M13/45 , H03M13/451 , H03M13/458
摘要： Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence.
摘要翻译：用于解码从非易失性固态存储器的存储器单元读取的数据的方法包括在软数据可用于解码器的时间之前尝试使用硬解码处理对硬数据进行解码。硬数据包括关于存储在存储器单元中的数字符号的信息，而没有数据置信度信息。软数据包括关于存储在存储单元中的数字符号和数据置信度的信息。响应于难以实现收敛的硬解码处理，在软数据变得可用于解码器之后，使用软解码处理解码软数据。在硬解码处理或软解码处理实现收敛之后，解码器生成解码数据的输出。

5. 发明申请

US20110296272A1 OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES 有权
标题翻译：固态存储器件的外部代码保护
公开(公告)号：US20110296272A1
公开(公告)日：2011-12-01
申请号：US12790120
申请日：2010-05-28
申请人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
发明人： Bernardo Rub , Ara Patapoutian , Arvind Sridharan , Bruce D. Buch
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： G06F11/1012
摘要： Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.
摘要翻译：外码字可以跨越存储器设备的多个数据块，多个芯片或多个芯片，以防止存储在块，芯片和/或芯片中的数据中的错误。固态存储器件被布置在多个数据块中，每个块包括以多页布置的存储器单元的阵列。数据被编码成内码字和基于符号的外码字。内码字和基于符号的外码字被存储在多个块的存储单元中。一个或多个内部码字被存储在每个块的每个页面中，并且每个外部码字的一个或多个符号被存储在每个块的至少一个页面中。内部码字和外部码字从存储器件读取并用于校正数据中的错误。

6. 发明授权

US08040994B1 Phase coefficient generation for PLL 有权
标题翻译： PLL的相位系数生成
公开(公告)号：US08040994B1
公开(公告)日：2011-10-18
申请号：US11688063
申请日：2007-03-19
申请人： Ara Patapoutian
发明人： Ara Patapoutian
IPC分类号： H03D3/24
CPC分类号： H03L7/1075
摘要： A method and apparatus is provided for synchronizing a clock signal by generating time varying PLL phase coefficients which approximate optimal PLL phase coefficients. An acquisition mode phase coefficient is determined by adding an error signal (A) to the sample counter (k) and finding the reciprocal of the result (1/(A+k)). The reciprocal can be calculated in hardware or determined by using a lookup table. A tracking mode phase coefficient is determined based on the error signal for use in the PLL during a track a tracking period. The tracking period begins when the tracking mode coefficient is greater than the acquisition mode coefficient.
摘要翻译：提供了一种通过产生近似最佳PLL相位系数的时变PLL相位系数来同步时钟信号的方法和装置。通过将采样计数器（k）的误差信号（A）相加并求出结果的倒数（1 /（A + k））来确定采集模式相位系数。可以用硬件计算倒数或使用查找表确定倒数。基于在跟踪期间的轨道期间在PLL中使用的误差信号来确定跟踪模式相位系数。当跟踪模式系数大于采集模式系数时，跟踪周期开始。

7. 发明授权

US07466782B1 Methods, apparatus and computer program products for determining the timing of bits based on frequency error 有权
标题翻译：用于基于频率误差确定位的时序的方法，装置和计算机程序产品
公开(公告)号：US07466782B1
公开(公告)日：2008-12-16
申请号：US10873103
申请日：2004-06-21
申请人： Ara Patapoutian
发明人： Ara Patapoutian
IPC分类号： G11B5/09
CPC分类号： G11B20/1403 , G11B5/09 , G11B20/10009 , G11B20/10037 , G11B20/10046 , G11B20/10222 , G11B20/10425 , G11B20/10481 , G11B2220/2516
摘要： Determining timing for bits in sampled data includes determining a bit error in the sampled data, determining a phase error in the sampled data, determining a frequency error of the sampled data based on the bit error and based on the phase error, and determining the timing for bits in the sampled data based on the determined frequency error.
摘要翻译：确定采样数据中的位的定时包括确定采样数据中的位错误，确定采样数据中的相位误差，基于位误差确定采样数据的频率误差，并根据相位误差确定定时用于基于所确定的频率误差的采样数据中的位。

8. 发明申请

US20070165325A1 Servo positioning adjustment 有权
标题翻译：伺服定位调整
公开(公告)号：US20070165325A1
公开(公告)日：2007-07-19
申请号：US11655799
申请日：2007-01-18
申请人： Ara Patapoutian , Zoran Coric
发明人： Ara Patapoutian , Zoran Coric
IPC分类号： G11B5/596
CPC分类号： G11B5/59627
摘要： An apparatus and associated method for observing an analog position signal of a control object in relation to positional indicia, recalling a previously stored runout correction value associated with the positional indicia, and calculating a corrected position signal for the control object in relation to the position signal and the runout correction value.
摘要翻译：一种用于观察与位置标记相关的控制对象的模拟位置信号的装置和相关联的方法，回收与该位置标记相关联的先前存储的跳动校正值，以及针对该位置信号计算控制对象的校正位置信号和跳动校正值。

9. 发明授权

US06882604B2 Method and apparatus for utilizing modulation codes that produce maximized sample timing information 有权
标题翻译：用于利用产生最大化采样定时信息的调制码的方法和装置
公开(公告)号：US06882604B2
公开(公告)日：2005-04-19
申请号：US09953845
申请日：2001-09-17
申请人： Ara Patapoutian , Peter McEwen
发明人： Ara Patapoutian , Peter McEwen
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , G11B20/18 , G11B7/00 , H04J13/02
CPC分类号： G11B20/10037 , G11B5/09 , G11B20/10009 , G11B20/10296 , G11B20/1403 , G11B20/1426 , G11B20/1833
摘要： The invention is a modulation system that encodes symbols in accordance with a modulation code which, for a given communications channel, produces a signal that at the decoder includes maximized sample timing information in each encoded symbol. For systems that use PLLs to control a sample timing clock, the sample timing information is the average or squared slope. The modulation code used for a given system is selected based on the target response h(x) of the associated communications channel, such that h (x)*rk exceeds a predetermined threshold value, where “*” represents convolution and rk is a modulation code symbol. To reduce the bit overhead, or code rate, the inventive modulation system provides more modulation code symbols at the start of a data block, or sector, when system jitter is expected to be relatively high in response, for example, to the movement of a read head. The system then includes fewer modulation code symbols later in the block, when the system jitter associated with a read or receive operation is reduced. The system thus provides sufficient timing information to minimize PLL jitter.
摘要翻译：本发明是一种调制系统，其根据调制码对符号进行编码，对于给定的通信信道，调制码产生一个在解码器处包括每个编码符号中的最大化采样定时信息的信号。对于使用PLL来控制采样定时时钟的系统，采样定时信息是平均或平方斜率。用于给定系统的调制码基于相关通信信道的目标响应h（x）被选择，使得h（x）* r≠k超过预定阈值，其中“* “表示卷积，r＆lt; k＆gt;是调制码符号。为了减少比特开销或码率，本发明的调制系统在数据块或扇区的开始处提供更多的调制码符号，当系统抖动被预期相对较高时，例如对于a的移动读头当与读取或接收操作相关联的系统抖动减小时，该系统随后在块中包括更少的调制码符号。因此，该系统提供足够的定时信息以最小化PLL抖动。

10. 发明授权

US06412088B1 Method and apparatus for using block reread 失效
标题翻译：使用块重读的方法和装置
公开(公告)号：US06412088B1
公开(公告)日：2002-06-25
申请号：US09453164
申请日：1999-12-02
申请人： Ara Patapoutian , Michael D. Leis , Mathew P. Vea
发明人： Ara Patapoutian , Michael D. Leis , Mathew P. Vea
IPC分类号： G11C2900
CPC分类号： G11B20/18 , G11B20/1876 , G11B2020/183
摘要： Disclosed is a method and apparatus for increasing the reliability of a disk drive. A block of information is read from a storage medium to provide a first sample, which is stored. The method determines whether an uncorrectable error occurred during the reading, and when the error is determined to have occurred, the block of information is reread from the storage medium to provide an averaged sample, and the average sample is decoded. Further disclosed is a storage unit, which includes a reader for reading a block of information from a storage medium to provide a first sample and for storing said first sample. An error determining mechanism determines whether an uncorrectable error occurred during the reading and issues a command to the reader to re-read the block of information to provide a second sample when the uncorrectable error is determined. A processor receives and averages the first sample and the second sample and produces an averaged sample. A decoder decodes the average sample.
摘要翻译：公开了一种用于增加磁盘驱动器的可靠性的方法和装置。从存储介质读取信息块以提供被存储的第一样本。该方法确定在读取期间是否发生不可纠正的错误，并且当确定发生错误时，从存储介质重新读取信息块以提供平均样本，并且对平均样本进行解码。进一步公开的是一种存储单元，其包括用于从存储介质读取信息块以提供第一样本并用于存储所述第一样本的读取器。错误确定机构确定在读取期间是否发生不可校正的错误，并且当确定不可校正的错误时向读者发出命令以重新读取信息块以提供第二样本。处理器接收并平均第一样品和第二样品并产生平均样品。解码器解码平均样本。

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