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    • 3. 发明授权
    • Multi-supply sequential logic unit
    • 多电源顺序逻辑单元
    • US08901819B2
    • 2014-12-02
    • US13992894
    • 2011-12-14
    • Arijit RaychowdhuryJaydeep P. KulkarniJames W. Tschanz
    • Arijit RaychowdhuryJaydeep P. KulkarniJames W. Tschanz
    • H03K19/0175
    • H03K19/017509G06F1/10G06F1/3296Y02D10/172
    • Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.
    • 这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置,方法和系统。 所述装置包括顺序单元,包括:数据路径,用于接收输入信号,包括在第一电源电平上操作的逻辑门,所述数据路径以产生输出信号; 以及时钟路径,包括用于在第二电源电平上操作的逻辑门,所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号,其中所述第二电源电平高于所述第一电力 供应水平。 该装置改善(即减少)顺序单元的建立时间,并允许处理器以最小工作电压(Vmin)运行,而不降低顺序单元的性能。
    • 4. 发明申请
    • SPIN TRANSFER TORQUE BASED MEMORY ELEMENTS FOR PROGRAMMABLE DEVICE ARRAYS
    • 用于可编程器件阵列的基于转子扭矩的记忆元件
    • US20140035617A1
    • 2014-02-06
    • US13997962
    • 2012-03-30
    • Arijit RaychowdhuryJames W. TschanzVivek De
    • Arijit RaychowdhuryJames W. TschanzVivek De
    • H03K19/177
    • H03K19/17728G11C11/16H03K19/177
    • Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.
    • 这里公开了使用基于高密度旋转转矩(STT)的存储器元件的半导体器件阵列,诸如现场可编程门阵列(FPGA)和复数可编程逻辑阵列(CPLAs)。 基于STT的存储器元件可以是独立的FPGA / CPLAs,或者可以嵌入在微处理器和/或数字信号处理(DSP)片上系统(SoC)中,以提供设计灵活性,以实现低功率,可扩展,安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身,所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动,消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要,安全性大大提高。