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    • 3. 发明申请
    • STORAGE CONTROLLER AND VIRTUAL VOLUME CONTROL METHOD
    • 存储控制器和虚拟体积控制方法
    • US20120173814A1
    • 2012-07-05
    • US13413166
    • 2012-03-06
    • Yutaro KawaguchiAtsushi IshikawaKatsuhiro Uchiumi
    • Yutaro KawaguchiAtsushi IshikawaKatsuhiro Uchiumi
    • G06F12/02
    • G06F3/0665G06F3/0605G06F3/061G06F3/0644G06F3/0647G06F3/067G06F11/1008G06F11/1076
    • A storage system includes a virtual volume, a plurality of RAID groups, a pool unit for managing a plurality of first real storage areas and a controller. If a write command related to the virtual volume is issued from a higher-level device, the controller selects a prescribed second real storage area from among respective second real storage areas included in a prescribed first real storage area, and associates this prescribed second real storage area with a prescribed area inside the virtual volume corresponding to the write command, and which associates one virtual volume with one first real storage area. A migration destination determination unit selects a migration-targeted second real storage area from among the respective second real storage areas associated with the virtual volume, and selects a migration-destination first real storage area, which is to become the migration destination of data stored in the migration-targeted second real storage area.
    • 存储系统包括虚拟卷,多个RAID组,用于管理多个第一实际存储区域的池单元和控制器。 如果从上级装置发出与虚拟卷有关的写入命令,则控制器从包括在规定的第一实际存储区域的各个第二实际存储区域中选择规定的第二实际存储区域,并将该规定的第二实际存储 具有与写入命令相对应的虚拟卷内的规定区域的区域,并且将一个虚拟卷与一个第一实际存储区域相关联。 移动目的地确定单元从与虚拟卷相关联的各个第二实际存储区域中选择迁移目标第二实际存储区域,并且选择迁移目的地第一实际存储区域,其将成为存储在其中的数据的迁移目的地 迁移目标第二实际存储区域。
    • 5. 发明授权
    • Integrated circuit device and electronic instrument
    • 集成电路器件和电子仪器
    • US08125269B2
    • 2012-02-28
    • US11545625
    • 2006-10-10
    • Hiroaki NomizoAtsushi IshikawaTsuyoshi Tamura
    • Hiroaki NomizoAtsushi IshikawaTsuyoshi Tamura
    • H03K17/687
    • H03K19/00361H01L27/0251
    • An integrated circuit device includes an I/O circuit which buffers and outputs an input signal D from a pad when an enable signal ENB is set at a second voltage level, a circuit block to which an output signal from the I/O circuit is input, and a malfunction prevention circuit which outputs to the circuit block an output signal QP of which a voltage level is set by a first power supply VDDC in a period T1 in which the signal ENB is set at a first voltage level and a period T2 including a period in which the signal ENB changes from the first voltage level to the second voltage level, and outputs to the circuit block the output signal QP corresponding to an output signal QI from the I/O circuit in a period T3 in which the signal ENB is set at the second voltage level.
    • 集成电路装置包括I / O电路,当使能信号ENB被设置在第二电压电平时,I / O电路缓冲并输出来自焊盘的输入信号D,输入来自I / O电路的输出信号的电路块 以及故障防止电路,其在信号ENB被设定为第一电压电平的期间T1中输出电路块中由第一电源VDDC设定电压电平的输出信号QP,以及包括 信号ENB从第一电压电平变化到第二电压电平的时段,并且在信号ENB的时段T3中向I / O电路输出对应于来自I / O电路的输出信号QI的输出信号QP 被设置在第二电压电平。
    • 10. 发明申请
    • Semiconductor device and method for manufacturing the same
    • US20080128804A1
    • 2008-06-05
    • US12009160
    • 2008-01-16
    • Atsushi Ishikawa
    • Atsushi Ishikawa
    • H01L27/088
    • H01L21/823892H01L21/761H01L21/823878H01L27/0928
    • A semiconductor device, comprising: a first transistor of a second electric conductivity type formed in a substrate including impurities of a first electric conductivity type; and a second transistor of the second electric conductivity type formed in the substrate, a source region of the second transistor being shared with a source region of the first transistor; wherein in a lower layer of a gate insulating film of the first transistor, a first offset layer of the second electric conductivity type is formed adjacent to a channel region of the first transistor, in a lower layer of a gate insulating film of the second transistor, a second offset layer of the second electric conductivity type is formed adjacent to a channel region of the second transistor, and in the source region, a first diffusion layer of the first electric conductivity type and a second diffusion layer of the first electric conductivity type in the upper layer of the first diffusion layer are formed, and wherein the second diffusion layer is provided so as to come in contact with the first and second offset layers via the first diffusion layer, and the impurity concentration of the first diffusion layer is higher than the impurity concentration of the substrate.