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1. 发明授权

US08136062B2 Hierarchy reassembler for 1×N VLSI design 有权
标题翻译： 1×N VLSI设计层次重组器
公开(公告)号：US08136062B2
公开(公告)日：2012-03-13
申请号：US12200016
申请日：2008-08-28
申请人： Paul M. Steinmetz , Benjamin J. Bowers , Anthony Correale, Jr. , Irfan Rashid , Matthew W. Baker
发明人： Paul M. Steinmetz , Benjamin J. Bowers , Anthony Correale, Jr. , Irfan Rashid , Matthew W. Baker
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist.
摘要翻译：公开了在闭环1×N系统中重新组合分层表示的实施例。一些实施例包括从1×N构建块的分层表示形成平坦网表，为平坦网表创建属性，以及例如通过逻辑设计工具的操作，改变平面网表的一个或多个元素，合成工具，物理设计工具或时序分析工具。实施例还包括生成反映改变的元素的1×N构建块的第二分层表示。另外的实施例包括具有1×N编译器和重组器的装置。 1×N编译器可以为1×N构建块的分层表示的元素的平坦网表创建属性。重组器可以使用这些属性来创建1×N构建块的第二层次表示，其反映元素的变化到平坦网表。

2. 发明申请

US20100107130A1 1XN BLOCK BUILDER FOR 1XN VLSI DESIGN 审中-公开
标题翻译： 1XN VLSI设计的1XN块建筑
公开(公告)号：US20100107130A1
公开(公告)日：2010-04-29
申请号：US12256594
申请日：2008-10-23
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Embodiments that generate 1×N building block representations for an IC design via a GUI of a 1×N block builder are disclosed. Some embodiments enable, via a GUI, selection of a logical function for a 1×N building block. The embodiments also comprise enabling selection of an implementation from a number of implementations of the logical function and automatically generating a 1×N building block representation of the logical function based on the selected implementation. The generated 1×N building block representation comprises an RTL description of the 1×N building block. Further embodiments comprise an apparatus having a GUI generator, a logical function selector to select a logical function, an implementation selector to select an implementation of the logical function from a number of implementations, and a 1×N building block generator to generate a 1×N building block representation of the 1×N building block based on the selected implementation.
摘要翻译：公开了通过1×N块构建器的GUI生成用于IC设计的1×N构建块表示的实施例。一些实施例通过GUI实现对1×N构建块的逻辑功能的选择。这些实施例还包括能够从逻辑功能的多个实现中选择实现，并且基于所选择的实现自动生成逻辑功能的1×N构建块表示。生成的1×N构建块表示包括1×N构建块的RTL描述。另外的实施例包括具有GUI生成器，用于选择逻辑功能的逻辑功能选择器，从多个实现中选择逻辑功能的实现的实现选择器的设备，以及1×N构建块生成器，以生成1× 基于所选实施的1×N构建块的N个构建块表示。

3. 发明申请

US20100058270A1 Hierarchy Reassembler for 1xN VLSI Design 有权
标题翻译： 1xN VLSI设计层次重组器
公开(公告)号：US20100058270A1
公开(公告)日：2010-03-04
申请号：US12200016
申请日：2008-08-28
申请人： Paul M. Steinmetz , Benjamin J. Bowers , Anthony Correale, JR. , Irfan Rashid , Matthew W. Baker
发明人： Paul M. Steinmetz , Benjamin J. Bowers , Anthony Correale, JR. , Irfan Rashid , Matthew W. Baker
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist.
摘要翻译：公开了在闭环1×N系统中重新组合分层表示的实施例。一些实施例包括从1×N构建块的分层表示形成平坦网表，为平坦网表创建属性，以及例如通过逻辑设计工具的操作，改变平面网表的一个或多个元素，合成工具，物理设计工具或时序分析工具。实施例还包括生成反映改变的元素的1×N构建块的第二分层表示。另外的实施例包括具有1×N编译器和重组器的装置。 1×N编译器可以为1×N构建块的分层表示的元素的平坦网表创建属性。重组器可以使用这些属性来创建1×N构建块的第二层次表示，其反映元素的变化到平面网表。

4. 发明申请

US20100058269A1 Uniquification and Parent-Child Constructs for 1xN VLSI Design 有权
标题翻译： 1xN VLSI设计的唯一性和父子构造
公开(公告)号：US20100058269A1
公开(公告)日：2010-03-04
申请号：US12201685
申请日：2008-08-29
申请人： Matthew W. Baker , Benjamin J. Bowers , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
发明人： Matthew W. Baker , Benjamin J. Bowers , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second 1×N building block. The association enables the first 1×N building block to inherit alterations of attributes of the second 1×N building block and enables unique alterations of attributes of the first 1×N building block which differ from the second 1×N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1×N building blocks, an attribute creator that creates a set of attributes and enables one of the 1×N building blocks to inherit parent attributes and comprise child attributes.
摘要翻译：公开了在闭环1×N系统中创建用于重新使用1×N构建块的父子关系的实施例。一些方法包括生成IC设计的表示，将第一个1×N构建块插入到该表示中，以及在第一个1×N构建块和第二个1×N构建块之间建立关联。该关联使得第一个1×N构建块能够继承第二个1×N构建块的属性的改变，并且使得与第二个1×N构建块不同的第一个1×N构建块的属性的唯一改变。另外的实施例包括具有等效确定器的装置，以确定两个1×N构建块之间的逻辑等价，创建一组属性的属性创建者，并且使得1×N构建块中的一个可以继承父属性并且包括子属性。

5. 发明授权

US08887113B2 Compiler for closed-loop 1xN VLSI design 有权
标题翻译：闭环1xN VLSI设计编译器
公开(公告)号：US08887113B2
公开(公告)日：2014-11-11
申请号：US13364249
申请日：2012-02-01
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
摘要翻译：公开了以闭环1×N方法设计使用1×N编译器的集成电路的实施例。一些实施例基于集成电路的设计的行为表示创建物理设计表示。行为表示可以包括具有一个或多个1×N构建块的RTL HDL。这些实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1×N构建块的元素。另外的实施例包括具有第一发生器以产生用于集成电路的设计的行为表示的装置，用于生成设计的逻辑表示的第二发生器，以及用于生成设计的物理设计表示的第三发生器，其中，表示生成器可以创建表示的更新版本，其反映对1×N构建块元素的改变。

6. 发明申请

US20120192129A1 Compiler for Closed-Loop 1xN VLSI Design 有权
公开(公告)号：US20120192129A1
公开(公告)日：2012-07-26
申请号：US13364256
申请日：2012-02-01
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

7. 发明申请

US20120190165A1 Creating Integrated Circuit Capacitance From Gate Array Structures 失效
标题翻译：从门阵列结构创建集成电路电容
公开(公告)号：US20120190165A1
公开(公告)日：2012-07-26
申请号：US13436993
申请日：2012-04-01
申请人： Anthony Correale, JR. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
发明人： Anthony Correale, JR. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
IPC分类号： H01L21/02
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了在集成电路内使用门阵列来形成电容结构的技术。实施例包括将P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列放置在集成电路设计中，将用于一个或多个P-fets和栅极的漏极和源耦合将一个或多个N-fets连接到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

8. 发明授权

US08141016B2 Integrated design for manufacturing for 1×N VLSI design 有权
标题翻译： 1×N VLSI设计的集成设计
公开(公告)号：US08141016B2
公开(公告)日：2012-03-20
申请号：US12201591
申请日：2008-08-29
申请人： Anthony Correale, Jr. , Benjamin J. Bowers , Matthew W. Baker , Irfan Rashid , Paul M. Steinmetz
发明人： Anthony Correale, Jr. , Benjamin J. Bowers , Matthew W. Baker , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12
摘要： Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.
摘要翻译：公开了通过闭环1×N编译器使DFM改变为1×N构建块的小区的实施例。一些实施例包括使用1×N编译器来检测1×N构建块的两个相邻小区之间的关系。基于该关系，实施例选择DFM改变，并将改变应用于物理设计表示。实施例可以根据关系来应用各种类型的DFM改变，例如添加多晶硅，添加金属以产生冗余连接，以及合并扩散区域以增加供应节点上的电容。另外的实施例包括具有细胞检查器以检查1×N构建块的两个相邻小区的装置，并确定两个小区的关系。该装置还包括一个DFM选择器，用于基于该关系选择DFM改变，并且DFM施加器将所选择的DFM改变应用于其中一个单元。

9. 发明申请

US20100155800A1 Creating Integrated Circuit Capacitance from Gate Array Structures 失效
标题翻译：从门阵列结构创建集成电路电容
公开(公告)号：US20100155800A1
公开(公告)日：2010-06-24
申请号：US12717605
申请日：2010-03-04
申请人： Anthony Correale, JR. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
发明人： Anthony Correale, JR. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
IPC分类号： H01L27/06 , H01L21/768
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了在集成电路内使用门阵列来形成电容结构的技术。实施例包括将P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列放置在集成电路设计中，将用于一个或多个P-fets和栅极的漏极和源耦合将一个或多个N-fets连接到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

10. 发明申请

US20100058271A1 Closed-Loop 1xN VLSI Design System 有权
标题翻译：闭环1xN VLSI设计系统
公开(公告)号：US20100058271A1
公开(公告)日：2010-03-04
申请号：US12200076
申请日：2008-08-28
申请人： Anthony Correale, JR. , Matthew W. Baker , Benjamin J. Bowers , Irfan Rashid , Paul M. Steinmetz
发明人： Anthony Correale, JR. , Matthew W. Baker , Benjamin J. Bowers , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Embodiments that design integrated circuits using a closed loop 1xN methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1xN building blocks. The embodiments may alter elements of the 1xN building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1xN compiler. The viewer may generate displays of behavioral representations of 1xN building blocks, with the behavioral representations comprising RTL definitions. The 1xN compiler may create physical design representations of the 1xN building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.
摘要翻译：公开了使用闭环1xN方法设计集成电路的实施例。一些实施例基于集成电路的设计的行为表示创建物理设计表示。行为表示可以包括具有一个或多个1xN构建块的RTL HDL。实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1xN构件的元件。另外的实施例包括具有观看者和1xN编译器的装置。观众可以生成1xN构建块的行为表示的显示，行为表示包括RTL定义。 1xN编译器可以创建1xN构建块的物理设计表示，并从物理设计表示中创建行为表示，其中物理设计表示具有由工具套件的一个或多个工具改变的元素。

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