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1. 发明申请

US20120192128A1 Compiler for Closed-Loop 1xN VLSI Design 有权
标题翻译：闭环1xN VLSI设计编译器
公开(公告)号：US20120192128A1
公开(公告)日：2012-07-26
申请号：US13364249
申请日：2012-02-01
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
摘要翻译：公开了以闭环1×N方法设计使用1×N编译器的集成电路的实施例。一些实施例基于集成电路的设计的行为表示创建物理设计表示。行为表示可以包括具有一个或多个1×N构建块的RTL HDL。这些实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1×N构建块的元素。另外的实施例包括具有第一发生器以产生用于集成电路的设计的行为表示的装置，用于生成设计的逻辑表示的第二发生器，以及用于生成设计的物理设计表示的第三发生器，其中，表示生成器可以创建表示的更新版本，其反映对1×N构建块元素的改变。

2. 发明授权

US08132134B2 Closed-loop 1×N VLSI design system 有权
标题翻译：闭环1×N VLSI设计系统
公开(公告)号：US08132134B2
公开(公告)日：2012-03-06
申请号：US12200076
申请日：2008-08-28
申请人： Anthony Correale, Jr. , Matthew W. Baker , Benjamin J. Bowers , Irfan Rashid , Paul M. Steinmetz
发明人： Anthony Correale, Jr. , Matthew W. Baker , Benjamin J. Bowers , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Embodiments that design integrated circuits using a closed loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1×N compiler. The viewer may generate displays of behavioral representations of 1×N building blocks, with the behavioral representations comprising RTL definitions. The 1×N compiler may create physical design representations of the 1×N building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.
摘要翻译：公开了使用闭环1×N方法设计集成电路的实施例。一些实施例基于集成电路的设计的行为表示创建物理设计表示。行为表示可以包括具有一个或多个1×N构建块的RTL HDL。这些实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1×N构建块的元素。另外的实施例包括具有观看者和1×N编译器的装置。观众可以生成1×N构建块的行为表示的显示，行为表示包括RTL定义。 1×N编译器可以创建1×N构建块的物理设计表示，并从物理设计表示创建行为表示，其中物理设计表示具有由工具套件的一个或多个工具改变的元素。

3. 发明授权

US07966598B2 Top level hierarchy wiring via 1×N compiler 有权
标题翻译：通过1×N编译器进行顶级层次布线
公开(公告)号：US07966598B2
公开(公告)日：2011-06-21
申请号：US12201643
申请日：2008-08-29
申请人： Anthony L. Polomik , Benjamin J. Bowers , Anthony Correale, Jr. , Matthew W. Baker , Irfan Rashid , Paul M. Steinmetz
发明人： Anthony L. Polomik , Benjamin J. Bowers , Anthony Correale, Jr. , Matthew W. Baker , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block.
摘要翻译：公开了使用1×N编译器的更高层布线信息路由1×N构建块的实施例。一些实施例包括确定1×N构建块的阻塞的高级坐标，通过较高级坐标确定针对阻塞形状的1×N坐标，并且创建1×N线内的1×N线避免1×N坐标的1×N构建块。另外的实施例包括具有更高级布线检查器以检查物理设计表示的1×N构建块附近的区域的更高级布线的装置。该装置还可以具有阻塞确定器，以确定影响1×N构建块的1×N布线的阻塞和用于计算阻塞形状的坐标的坐标计算器，其中所计算的坐标可以使路由工具为1×N构建块创建1×N线路时避免形状。

4. 发明申请

US20050242924A1 Method and apparatus for resisting hardware hacking through internal register interface 有权
标题翻译：通过内部寄存器接口抵抗硬件黑客的方法和装置
公开(公告)号：US20050242924A1
公开(公告)日：2005-11-03
申请号：US10835462
申请日：2004-04-29
申请人： Paul Yosim , Irfan Rashid
发明人： Paul Yosim , Irfan Rashid
IPC分类号： G06F21/00 , H04Q1/00 , G05B19/00
CPC分类号： G06F21/71 , G06F2221/2105
摘要： Methods and apparatus that allow restricted access to internal registers of an integrated circuit (IC) device via an interface are provided. Unrestricted access to internal registers via the interface may be allowed during a manufacturing process to allow device testing. After such testing is complete, the device may be placed in a restricted access mode, for example, by blowing a master “lock” fuse, to prevent unrestricted access to one or more of the internal registers via the interface. However, full or partial access to the internal registers may still be provided via an access code or “combination lock” allowing the master fuse lock, in effect, to be bypassed.
摘要翻译：提供允许通过接口限制访问集成电路（IC）设备的内部寄存器的方法和装置。允许在制造过程中允许通过接口对内部寄存器的无限制访问，以允许设备测试。在这样的测试完成之后，例如可以通过吹动主“锁定”保险丝来将设备置于受限制的访问模式中，以防止经由接口对一个或多个内部寄存器的不受限制的访问。然而，仍然可以通过访问代码或“组合锁”来提供对内部寄存器的全部或部分访问，从而实现主旁路的主熔丝锁定。

5. 发明授权

US08887113B2 Compiler for closed-loop 1xN VLSI design 有权
标题翻译：闭环1xN VLSI设计编译器
公开(公告)号：US08887113B2
公开(公告)日：2014-11-11
申请号：US13364249
申请日：2012-02-01
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
摘要翻译：公开了以闭环1×N方法设计使用1×N编译器的集成电路的实施例。一些实施例基于集成电路的设计的行为表示创建物理设计表示。行为表示可以包括具有一个或多个1×N构建块的RTL HDL。这些实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1×N构建块的元素。另外的实施例包括具有第一发生器以产生用于集成电路的设计的行为表示的装置，用于生成设计的逻辑表示的第二发生器，以及用于生成设计的物理设计表示的第三发生器，其中，表示生成器可以创建表示的更新版本，其反映对1×N构建块元素的改变。

6. 发明申请

US20120192129A1 Compiler for Closed-Loop 1xN VLSI Design 有权
公开(公告)号：US20120192129A1
公开(公告)日：2012-07-26
申请号：US13364256
申请日：2012-02-01
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

7. 发明授权

US08141016B2 Integrated design for manufacturing for 1×N VLSI design 有权
标题翻译： 1×N VLSI设计的集成设计
公开(公告)号：US08141016B2
公开(公告)日：2012-03-20
申请号：US12201591
申请日：2008-08-29
申请人： Anthony Correale, Jr. , Benjamin J. Bowers , Matthew W. Baker , Irfan Rashid , Paul M. Steinmetz
发明人： Anthony Correale, Jr. , Benjamin J. Bowers , Matthew W. Baker , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12
摘要： Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.
摘要翻译：公开了通过闭环1×N编译器使DFM改变为1×N构建块的小区的实施例。一些实施例包括使用1×N编译器来检测1×N构建块的两个相邻小区之间的关系。基于该关系，实施例选择DFM改变，并将改变应用于物理设计表示。实施例可以根据关系来应用各种类型的DFM改变，例如添加多晶硅，添加金属以产生冗余连接，以及合并扩散区域以增加供应节点上的电容。另外的实施例包括具有细胞检查器以检查1×N构建块的两个相邻小区的装置，并确定两个小区的关系。该装置还包括一个DFM选择器，用于基于该关系选择DFM改变，并且DFM施加器将所选择的DFM改变应用于其中一个单元。

8. 发明申请

US20100058271A1 Closed-Loop 1xN VLSI Design System 有权
标题翻译：闭环1xN VLSI设计系统
公开(公告)号：US20100058271A1
公开(公告)日：2010-03-04
申请号：US12200076
申请日：2008-08-28
申请人： Anthony Correale, JR. , Matthew W. Baker , Benjamin J. Bowers , Irfan Rashid , Paul M. Steinmetz
发明人： Anthony Correale, JR. , Matthew W. Baker , Benjamin J. Bowers , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Embodiments that design integrated circuits using a closed loop 1xN methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1xN building blocks. The embodiments may alter elements of the 1xN building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a viewer and a 1xN compiler. The viewer may generate displays of behavioral representations of 1xN building blocks, with the behavioral representations comprising RTL definitions. The 1xN compiler may create physical design representations of the 1xN building block and create behavioral representations from the physical design representations, wherein the physical design representations have elements altered by one or more tools of a tool suite.
摘要翻译：公开了使用闭环1xN方法设计集成电路的实施例。一些实施例基于集成电路的设计的行为表示创建物理设计表示。行为表示可以包括具有一个或多个1xN构建块的RTL HDL。实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1xN构件的元件。另外的实施例包括具有观看者和1xN编译器的装置。观众可以生成1xN构建块的行为表示的显示，行为表示包括RTL定义。 1xN编译器可以创建1xN构建块的物理设计表示，并从物理设计表示中创建行为表示，其中物理设计表示具有由工具套件的一个或多个工具改变的元素。

9. 发明授权

US08136062B2 Hierarchy reassembler for 1×N VLSI design 有权
标题翻译： 1×N VLSI设计层次重组器
公开(公告)号：US08136062B2
公开(公告)日：2012-03-13
申请号：US12200016
申请日：2008-08-28
申请人： Paul M. Steinmetz , Benjamin J. Bowers , Anthony Correale, Jr. , Irfan Rashid , Matthew W. Baker
发明人： Paul M. Steinmetz , Benjamin J. Bowers , Anthony Correale, Jr. , Irfan Rashid , Matthew W. Baker
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Embodiments that reassemble hierarchical representations in a closed-loop 1×N system are disclosed. Some embodiments comprise creating a flat netlist from a hierarchical representation of a 1×N building block, creating attributes for the flat netlist, and altering one or more elements of the flat netlist, such as by an operation of a logic design tool, a synthesis tool, a physical design tool, or a timing analysis tool. The embodiments further comprise generating a second hierarchical representation of the 1×N building block that reflects the altered element. Further embodiments comprise an apparatus having a 1×N compiler and a reassembler. The 1×N compiler may create attributes for a flat netlist of elements of a hierarchical representation of a 1×N building block. The reassembler may use the attributes to create a second hierarchical representation of the 1×N building block that reflects alteration of elements to the flat netlist.
摘要翻译：公开了在闭环1×N系统中重新组合分层表示的实施例。一些实施例包括从1×N构建块的分层表示形成平坦网表，为平坦网表创建属性，以及例如通过逻辑设计工具的操作，改变平面网表的一个或多个元素，合成工具，物理设计工具或时序分析工具。实施例还包括生成反映改变的元素的1×N构建块的第二分层表示。另外的实施例包括具有1×N编译器和重组器的装置。 1×N编译器可以为1×N构建块的分层表示的元素的平坦网表创建属性。重组器可以使用这些属性来创建1×N构建块的第二层次表示，其反映元素的变化到平坦网表。

10. 发明申请

US20100107130A1 1XN BLOCK BUILDER FOR 1XN VLSI DESIGN 审中-公开
标题翻译： 1XN VLSI设计的1XN块建筑
公开(公告)号：US20100107130A1
公开(公告)日：2010-04-29
申请号：US12256594
申请日：2008-10-23
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, JR. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Embodiments that generate 1×N building block representations for an IC design via a GUI of a 1×N block builder are disclosed. Some embodiments enable, via a GUI, selection of a logical function for a 1×N building block. The embodiments also comprise enabling selection of an implementation from a number of implementations of the logical function and automatically generating a 1×N building block representation of the logical function based on the selected implementation. The generated 1×N building block representation comprises an RTL description of the 1×N building block. Further embodiments comprise an apparatus having a GUI generator, a logical function selector to select a logical function, an implementation selector to select an implementation of the logical function from a number of implementations, and a 1×N building block generator to generate a 1×N building block representation of the 1×N building block based on the selected implementation.
摘要翻译：公开了通过1×N块构建器的GUI生成用于IC设计的1×N构建块表示的实施例。一些实施例通过GUI实现对1×N构建块的逻辑功能的选择。这些实施例还包括能够从逻辑功能的多个实现中选择实现，并且基于所选择的实现自动生成逻辑功能的1×N构建块表示。生成的1×N构建块表示包括1×N构建块的RTL描述。另外的实施例包括具有GUI生成器，用于选择逻辑功能的逻辑功能选择器，从多个实现中选择逻辑功能的实现的实现选择器的设备，以及1×N构建块生成器，以生成1× 基于所选实施的1×N构建块的N个构建块表示。

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