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1. 发明授权

US08739086B2 Compiler for closed-loop 1×N VLSI design 有权
标题翻译：闭环1×N VLSI设计编译器
公开(公告)号：US08739086B2
公开(公告)日：2014-05-27
申请号：US13364256
申请日：2012-02-01
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
摘要翻译：公开了以闭环1×N方法设计使用1×N编译器的集成电路的实施例。一些实施例基于集成电路的设计的行为表示创建物理设计表示。行为表示可以包括具有一个或多个1×N构建块的RTL HDL。这些实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1×N构建块的元素。另外的实施例包括具有第一发生器以产生用于集成电路的设计的行为表示的装置，用于生成设计的逻辑表示的第二发生器，以及用于生成设计的物理设计表示的第三发生器，其中，表示生成器可以创建表示的更新版本，其反映对1×N构建块元素的改变。

2. 发明授权

US08122399B2 Compiler for closed-loop 1×N VLSI design 有权
标题翻译：闭环1×N VLSI设计编译器
公开(公告)号：US08122399B2
公开(公告)日：2012-02-21
申请号：US12200121
申请日：2008-08-28
申请人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
发明人： Benjamin J. Bowers , Matthew W. Baker , Anthony Correale, Jr. , Irfan Rashid , Paul M. Steinmetz
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F17/5081
摘要： Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.
摘要翻译：公开了以闭环1×N方法设计使用1×N编译器的集成电路的实施例。一些实施例基于集成电路的设计的行为表示创建物理设计表示。行为表示可以包括具有一个或多个1×N构建块的RTL HDL。这些实施例可以通过使用逻辑设计工具，综合工具，物理设计工具和时序分析工具来改变1×N构建块的元素。另外的实施例包括具有第一发生器以产生用于集成电路的设计的行为表示的装置，用于生成设计的逻辑表示的第二发生器，以及用于生成设计的物理设计表示的第三发生器，其中，表示生成器可以创建表示的更新版本，其反映对1×N构建块元素的改变。

3. 发明授权

US07919819B2 Interconnect components of a semiconductor device 失效
标题翻译：半导体器件的互连部件
公开(公告)号：US07919819B2
公开(公告)日：2011-04-05
申请号：US12351015
申请日：2009-01-09
申请人： Anthony Correale, Jr.
发明人： Anthony Correale, Jr.
IPC分类号： H01L29/72
CPC分类号： H01L27/0207 , H01L27/11807
摘要： Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.
摘要翻译：实施例包括经调整的多晶硅栅极间距与金属线间距关系，以改善面积标量，同时增加具有固定多晶硅栅极间距的ACLV容差。在一些实施例中，调整用于至少一个金属化层的导线间距以匹配多晶硅栅极的间距。在一个实施例中，与用于访问互连电池结构的输入或输出的用于与多晶硅栅极相同的取向运行的最低金属化层的下一个被放宽以匹配最小接触栅极间距，并且金属在每个多晶硅门。在另一个实施例中，多晶硅栅极间距可以被放宽以获得较小的最小公倍数，同时集成电路的导线间距可以减小最小偏移。

4. 发明授权

US07908571B2 Systems and media to improve manufacturability of semiconductor devices 有权
标题翻译：系统和介质，以提高半导体器件的可制造性
公开(公告)号：US07908571B2
公开(公告)日：2011-03-15
申请号：US11971171
申请日：2008-01-08
申请人： Benjamin J. Bowers , Anthony Correale, Jr.
发明人： Benjamin J. Bowers , Anthony Correale, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/12 , Y02P90/265
摘要： Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.
摘要翻译：公开了用于提高集成电路单元内的单元和结构的可制造性的方法，系统和介质。实施例包括布置可编程单元，布线可编程单元，分析单元布置并互连布线以用于制造改进机会的方法，以及修改可编程单元结构以结合制造改进。在一些实施例中，布线以防止短路。在其他实施例中，通过向周围的触点和通孔附加额外的金属化，或通过添加冗余的触点和通孔来改善触点和通孔的可靠性。在一个实施例中，以迭代方式对集成电路单元进行一系列制造改进。

5. 发明授权

US07728362B2 Creating integrated circuit capacitance from gate array structures 失效
标题翻译：从门阵列结构创建集成电路电容
公开(公告)号：US07728362B2
公开(公告)日：2010-06-01
申请号：US11337010
申请日：2006-01-20
申请人： Anthony Correale, Jr. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
发明人： Anthony Correale, Jr. , Benjamin J. Bowers , Douglass T. Lamb , Nishith Rohatgi
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/11898 , H01L28/40
摘要： Using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise having a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.
摘要翻译：公开了使用门阵列来在集成电路内形成电容结构。实施例包括在集成电路设计中具有P型场效应晶体管（P-fets）和N型场效应晶体管（N-fets）的栅极阵列，将用于一个或多个P-fets和栅极的漏极和源耦合将一个或多个N-fets连接到电源地，以及将一个或多个P-fets的栅极和用于一个或多个N-fets的漏极和源耦合到电源的正电压。在一些实施例中，通过将一个或多个P-fets和一个或多个N-fets分别偏置到正电压和地电位，P-fets和N-fets的电容式设备的源极到漏极泄漏电流被最小化。在其他实施例中，可以使用可熔元件实现电容结构，以在短路的情况下隔离电容结构。

6. 发明申请

US20090114952A1 Interconnect Components of a Semiconductor Device 失效
标题翻译：半导体器件的互连元件
公开(公告)号：US20090114952A1
公开(公告)日：2009-05-07
申请号：US12351015
申请日：2009-01-09
申请人： Anthony Correale, JR.
发明人： Anthony Correale, JR.
IPC分类号： H01L25/065
CPC分类号： H01L27/0207 , H01L27/11807
摘要： Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.
摘要翻译：实施例包括经调整的多晶硅栅极间距与金属线间距关系，以改善面积标量，同时增加具有固定多晶硅栅极间距的ACLV容差。在一些实施例中，调整用于至少一个金属化层的导线间距以匹配多晶硅栅极的间距。在一个实施例中，与用于访问互连电池结构的输入或输出的用于与多晶硅栅极相同的取向运行的最低金属化层的下一个被放宽以匹配最小接触栅极间距，并且金属在每个多晶硅门。在另一个实施例中，多晶硅栅极间距可以被放宽以获得较小的最小公倍数，同时集成电路的导线间距可以减小最小偏移。

7. 发明申请

US20090032903A1 MULTIPLE VOLTAGE INTEGRATED CIRCUIT AND DESIGN METHOD THEREFOR 审中-公开
标题翻译：多电压集成电路及其设计方法
公开(公告)号：US20090032903A1
公开(公告)日：2009-02-05
申请号：US12251195
申请日：2008-10-14
申请人： Anthony Correale, JR. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
发明人： Anthony Correale, JR. , David S. Kung , Douglass T. Lamb , Zhigang Pan , Ruchir Puri , David Wallach
IPC分类号： H01L29/00
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/78 , H01L27/118
摘要： An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.
摘要翻译：一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。电路行可以包括由低电压（Vdd1）电源供电的低压岛和由高电压（Vddh）电源供电的高压岛。包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。电平转换器可以放置高压电路元件。

8. 发明申请

US20090019264A1 ADAPTIVE EXECUTION CYCLE CONTROL METHOD FOR ENHANCED INSTRUCTION THROUGHPUT 失效
标题翻译：自适应执行循环控制方法，用于增强指导性
公开(公告)号：US20090019264A1
公开(公告)日：2009-01-15
申请号：US11776121
申请日：2007-07-11
申请人： Anthony Correale, JR. , Kenichi Tsuchiya
发明人： Anthony Correale, JR. , Kenichi Tsuchiya
IPC分类号： G06F9/30
CPC分类号： G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/3836 , G06F9/3869 , Y02D10/126
摘要： A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is scheduled to be executed. The logic then automatically changes an execution cycle frequency of the specific pipeline stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the particular-type instructions. The cycle frequency of only the one or more functional stages are switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline. The logic also automatically switches the execution cycle frequency of the specific pipeline stages back from the second, higher cycle frequency to the first cycle frequency, when the number of scheduled first-type instructions has completed execution.
摘要翻译：一种用于增加处理器中的指令吞吐量的方法，系统和处理器，其执行指令流水线内的较长延迟指令。与执行流水线的特定阶段相关联的逻辑负责执行特定类型的指令，确定何时调度执行特定类型指令的至少一个阈值数目。逻辑然后自动地将特定流水线级的执行周期频率从第一周期频率改变到第二预先建立的较高周期频率，这使得能够更有效地执行特定类型指令的执行吞吐量。只有一个或多个功能级的周期频率被切换到与处理器管线中的其他功能级的周期频率无关的较高周期频率。当调度的第一类型指令的数量已经完成执行时，逻辑还自动将特定流水线级的执行周期频率从第二较高周期频率切换到第一周期频率。

9. 发明授权

US06900662B2 Level translator circuit for power supply disablement 失效
标题翻译：电源禁用电平转换电路
公开(公告)号：US06900662B2
公开(公告)日：2005-05-31
申请号：US10439362
申请日：2003-05-16
申请人： Anthony Correale, Jr.
发明人： Anthony Correale, Jr.
IPC分类号： H03K3/356 , H03K19/094
CPC分类号： H03K3/356113
摘要： A level translator circuit for use between a transmitting voltage potential circuit and a receiving voltage potential circuit is disclosed. The translator circuit includes a first transistor coupled to the transmitting voltage potential circuit and a clamping mechanism coupled to the first transistor. The circuit also includes a second transistor coupled to the first transistor, a higher voltage potential and the receiving voltage potential circuit. The circuit includes a third transistor coupled to the receiving voltage potential circuit, the higher voltage potential and the second transistor. Finally, the circuit includes a fourth transistor coupled to the receiving voltage potential circuit, and to a ground potential. The clamping mechanism clamps the input of the translator circuit such than an appropriate logic level is provided to the receiving voltage potential circuit and the leakage current is minimized when the transmitting voltage potential circuit is disabled. Accordingly, a level translator circuit is provided that operates effectively even when the transmitting voltage potential circuit is disabled. In addition, leakage current is minimized for the two distinct power supplies by clamping the input of the circuit such that an appropriate logical level is provided at the output of the circuit.
摘要翻译：公开了一种在发射电压电位电路和接收电压电位电路之间使用的电平转换器电路。转换器电路包括耦合到发射电压电位电路的第一晶体管和耦合到第一晶体管的钳位机构。该电路还包括耦合到第一晶体管的第二晶体管，较高电压电位和接收电压电位电路。该电路包括耦合到接收电压电位电路的第三晶体管，较高电压电位和第二晶体管。最后，电路包括耦合到接收电压电位电路的第四晶体管和接地电位。钳位机构夹持转换器电路的输入，这样，当接收电压电位电路提供适当的逻辑电平时，当禁止发射电压电位电路时，钳位电路的漏电流最小。因此，提供了一种电平转换器电路，即使当禁止发射电压电位电路时也能有效地工作。此外，通过钳位电路的输入使得在电路的输出处提供适当的逻辑电平，对于两个不同的电源，泄漏电流被最小化。

10. 发明授权

US06593789B2 Precise and programmable duty cycle generator 有权
标题翻译：精确和可编程的占空比发电机
公开(公告)号：US06593789B2
公开(公告)日：2003-07-15
申请号：US10020528
申请日：2001-12-14
申请人： Francois I. Atallah , Anthony Correale, Jr. , David J. Seman , Richard D. Tax
发明人： Francois I. Atallah , Anthony Correale, Jr. , David J. Seman , Richard D. Tax
IPC分类号： H03K3017
CPC分类号： H03K5/1565 , H03K2005/00039
摘要： A precise and programmable duty cycle generator which can produce a user definable duty cycle clock signal with precision. This circuit is comprised of a number of generally known circuit elements such as a digital to analog converter (DAC), low pass filter (LPF) and operational transconductance amplifier (OTA), as well as a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit is unique and employs a number of stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. The current starved inverters are controlled by a single voltage, which causes the current starved inverter's delay to degrade/improve on only one transition to effect a change in the duty cycle. For improved precision, a differential embodiment employs the same VCDCG.
摘要翻译：精确可编程的占空比发生器，可以精确地产生用户定义的占空比时钟信号。该电路包括许多通常已知的电路元件，例如数模转换器（DAC），低通滤波器（LPF）和运算跨导放大器（OTA），以及独特的电压控制占空比发生器（VCDCG）。该电路能够在宽范围的工作频率上产生精确的用户可编程占空比时钟信号。 VCDCG电路是独一无二的，采用多个阶段，每个阶段都有一个现有的饥饿逆变器，紧随其后的是常规逆变器，以允许占空比校正是加法或减法。目前的饥饿逆变器由单一电压控制，这导致当前饥饿的逆变器的延迟仅在一个转换中降级/改善，以实现占空比的变化。为了提高精度，差分实施例采用相同的VCDCG。

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