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1. 发明申请

US20120167107A1 Power Managed Lock Optimization 有权
标题翻译：电力管理锁优化
公开(公告)号：US20120167107A1
公开(公告)日：2012-06-28
申请号：US13413796
申请日：2012-03-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F9/46
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

2. 发明授权

US08332559B2 Power managed lock optimization 有权
标题翻译：电源管理锁优化
公开(公告)号：US08332559B2
公开(公告)日：2012-12-11
申请号：US13413796
申请日：2012-03-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

3. 发明授权

US08156275B2 Power managed lock optimization 有权
公开(公告)号：US08156275B2
公开(公告)日：2012-04-10
申请号：US12465182
申请日：2009-05-13
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

4. 发明申请

US20100293401A1 Power Managed Lock Optimization 有权
标题翻译：电力管理锁优化
公开(公告)号：US20100293401A1
公开(公告)日：2010-11-18
申请号：US12465182
申请日：2009-05-13
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

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