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1. 发明申请

US20120167107A1 Power Managed Lock Optimization 有权
标题翻译：电力管理锁优化
公开(公告)号：US20120167107A1
公开(公告)日：2012-06-28
申请号：US13413796
申请日：2012-03-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F9/46
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

2. 发明授权

US08332559B2 Power managed lock optimization 有权
标题翻译：电源管理锁优化
公开(公告)号：US08332559B2
公开(公告)日：2012-12-11
申请号：US13413796
申请日：2012-03-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

3. 发明授权

US08156275B2 Power managed lock optimization 有权
公开(公告)号：US08156275B2
公开(公告)日：2012-04-10
申请号：US12465182
申请日：2009-05-13
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

4. 发明申请

US20100293401A1 Power Managed Lock Optimization 有权
标题翻译：电力管理锁优化
公开(公告)号：US20100293401A1
公开(公告)日：2010-11-18
申请号：US12465182
申请日：2009-05-13
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

5. 发明申请

US20120297096A1 Data Flow Control Within and Between DMA Channels 有权
标题翻译： DMA通道内和之间的数据流控制
公开(公告)号：US20120297096A1
公开(公告)日：2012-11-22
申请号：US13563127
申请日：2012-07-31
申请人： Dominic Go , Mark D. Hayter , Puneet Kumar
发明人： Dominic Go , Mark D. Hayter , Puneet Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。每个正在使用的DMA通道都有一个数据结构。数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

6. 发明授权

US08266338B2 Data flow control within and between DMA channels 有权
标题翻译： DMA通道内和之间的数据流控制
公开(公告)号：US08266338B2
公开(公告)日：2012-09-11
申请号：US13276537
申请日：2011-10-19
申请人： Dominic Go , Mark D. Hayter , Puneet Kumar
发明人： Dominic Go , Mark D. Hayter , Puneet Kumar
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.
摘要翻译：在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。每个正在使用的DMA通道都有一个数据结构。数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

7. 发明授权

US07783515B1 Itemized receipt tracking system 有权
标题翻译：分类收据跟踪系统
公开(公告)号：US07783515B1
公开(公告)日：2010-08-24
申请号：US12413324
申请日：2009-03-27
申请人： Puneet Kumar , Debashis Ghosh , Matthew Brian Cincera , Sudeshna Banerjee
发明人： Puneet Kumar , Debashis Ghosh , Matthew Brian Cincera , Sudeshna Banerjee
IPC分类号： G06Q20/00 , G06Q40/00 , G06Q30/00 , G06F17/30
CPC分类号： G06Q20/10 , G06Q10/10 , G06Q20/0453 , G06Q20/102 , G06Q20/1085 , G06Q20/20 , G06Q30/06 , G06Q30/0633 , G06Q40/00
摘要： Embodiments of the present invention are directed to apparatuses, systems, methods, and computer program products for: (1) receiving transaction data from a transaction involving a consumer, where the transaction data comprises product-level information; (2) storing the transaction data in memory; and/or (3) posting the transaction data to an account accessible to the consumer.
摘要翻译：本发明的实施例涉及用于：（1）从涉及消费者的交易接收交易数据的装置，系统，方法和计算机程序产品，其中交易数据包括产品级信息; （2）将交易数据存储在存储器中; 和/或（3）将交易数据发布到消费者可访问的帐户。

8. 发明申请

US20090119488A1 Prefetch Unit 有权
标题翻译：预取单元
公开(公告)号：US20090119488A1
公开(公告)日：2009-05-07
申请号：US12350020
申请日：2009-01-07
申请人： Sudarshan Kadambi , Puneet Kumar , Po-Yung Chang
发明人： Sudarshan Kadambi , Puneet Kumar , Po-Yung Chang
IPC分类号： G06F9/06
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/3455 , G06F9/383 , G06F2212/6028
摘要： In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.
摘要翻译：在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。预取单元被配置为同时维护多个单独的活动预取流。每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

9. 发明授权

US06332175B1 Low power system and method for playing compressed audio data 有权
标题翻译：用于播放压缩音频数据的低功率系统和方法
公开(公告)号：US06332175B1
公开(公告)日：2001-12-18
申请号：US09249183
申请日：1999-02-12
申请人： Andrew Birrell , William Laing , Puneet Kumar
发明人： Andrew Birrell , William Laing , Puneet Kumar
IPC分类号： G06F1200
CPC分类号： G11B20/10527 , G11B20/00007 , G11B27/034 , G11B27/105 , G11B27/11 , G11B27/34 , G11B2020/10768 , G11B2220/20 , G11B2220/2545 , G11B2220/65
摘要： A portable audio player stores a large amount of compressed audio data on an internal disk drive, and loads a portion of this into an internal random access memory (RAM) which requires less power and less time to access. The audio player plays the data stored in RAM and monitors the amount of unplayed data. When the amount of unplayed data falls below a threshold, additional data is copied from the disk drive into RAM. Because the time necessary to copy a block of data from the disk drive to RAM is much less than the amount of time it takes to play the same block of audio data from RAM, this approach minimizes the amount of time that the disk drive must be operated, and thus minimizes the amount of power consumed by the system.
摘要翻译：便携式音频播放器将大量的压缩音频数据存储在内部磁盘驱动器上，并将其一部分加载到需要更少功率和更少访问时间的内部随机存取存储器（RAM）中。音频播放器播放存储在RAM中的数据，并监视未播放数据的数量。当未播放数据量低于阈值时，附加数据将从磁盘驱动器复制到RAM中。由于将数据块从磁盘驱动器复制到RAM所需的时间远远少于从RAM中播放同一块音频数据所需的时间，因此该方法可最大限度地减少磁盘驱动器必须的时间操作，从而最小化系统消耗的功率量。

10. 发明申请

US20170044183A1 FACTOR XIa INHIBITORS 审中-公开
标题翻译：因子XIA抑制剂
公开(公告)号：US20170044183A1
公开(公告)日：2017-02-16
申请号：US15305421
申请日：2015-04-21
申请人： Yeon-Hee Lim , Zhuyan Guo , Amjad Ali , Scott D. Edmondson , Weiguo Liu , Giocanda V. Gallo-Etienne , Heping Wu , Ying-Duo Gao , Andrew W. Stamford , Younong Yu , Nancy J. Kevin , Rajan Anand , Deyou Sha , Santhosh F. Neelamkavil , Zahid Hussain , Puneet Kumar , Remond Moningka , Joseph L. Duffy , Jiayi Xu , Yu Jiang , Anjan Chakrabarti , Hiroki Sone
发明人： Yeon-Hee Lim , Zhuyan Guo , Amjad Ali , Scott D. Edmondson , Weiguo Liu , Giocanda V. Gallo-Etienne , Heping Wu , Ying-Duo Gao , Andrew W. Stamford , Younong Yu , Nancy J. Kevin , Rajan Anand , Deyou Sha , Santhosh F. Neelamkavil , Zahid Hussain , Puneet Kumar , Remond Moningka , Joseph L. Duffy , Jiayi Xu , Yu Jiang , Anjan Chakrabarti , Hiroki Sone
IPC分类号： C07D498/20 , C07F9/6561 , C07D487/10 , C07D498/10 , C07D471/10
CPC分类号： C07D498/20 , C07D471/10 , C07D487/10 , C07D498/10 , C07F9/6561
摘要： The present invention provides a compound of Formula (I) and pharmaceutical compositions comprising one or more said compounds, and methods for using said compounds for treating or preventing thromboses, embolisms, hypercoagulability or fibrotic changes. The compounds are selective Factor XIa inhibitors or dual inhibitors of Factor XIa and plasma kallikrein.
摘要翻译：本发明提供式（I）的化合物和包含一种或多种所述化合物的药物组合物，以及使用所述化合物治疗或预防血栓形成，栓塞，高凝状态或纤维变化的方法。该化合物是选择性因子XIa抑制剂或因子XIa和血浆激肽释放酶的双重抑制剂。

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