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1. 发明申请

US20120167107A1 Power Managed Lock Optimization 有权
标题翻译：电力管理锁优化
公开(公告)号：US20120167107A1
公开(公告)日：2012-06-28
申请号：US13413796
申请日：2012-03-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F9/46
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

2. 发明授权

US08332559B2 Power managed lock optimization 有权
标题翻译：电源管理锁优化
公开(公告)号：US08332559B2
公开(公告)日：2012-12-11
申请号：US13413796
申请日：2012-03-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

3. 发明授权

US08156275B2 Power managed lock optimization 有权
公开(公告)号：US08156275B2
公开(公告)日：2012-04-10
申请号：US12465182
申请日：2009-05-13
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

4. 发明申请

US20100293401A1 Power Managed Lock Optimization 有权
标题翻译：电力管理锁优化
公开(公告)号：US20100293401A1
公开(公告)日：2010-11-18
申请号：US12465182
申请日：2009-05-13
申请人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
发明人： Josh P. de Cesare , Ruchi Wadhawan , Michael J. Smith , Puneet Kumar , Bernard J. Semeria
IPC分类号： G06F1/32
CPC分类号： G06F1/3228 , G06F9/526
摘要： In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.
摘要翻译：在一个实施例中，可以提供可以被编程到所选择的时间间隔或唤醒间隔的定时器单元。处理器可以执行等待事件指令，并为包括指令的线程输入低功率状态。定时器单元可以在唤醒间隔期满时发送定时器事件，并且处理器可以响应于定时器事件而退出低功率状态。线程可以在等待事件指令之后的指令继续执行。在一个实施例中，处理器/定时器单元可以用于实现功率管理的锁获取机制，其中处理器被唤醒多次以检查锁定并且如果锁不是空闲的则执行等待事件指令，之后，线程可能会阻塞，直到锁定为空。

5. 发明授权

US08959270B2 Interrupt distribution scheme 有权
标题翻译：中断分配方案
公开(公告)号：US08959270B2
公开(公告)日：2015-02-17
申请号：US12962146
申请日：2010-12-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Erik P. Machnicki , Mark D. Hayter
发明人： Josh P. de Cesare , Ruchi Wadhawan , Erik P. Machnicki , Mark D. Hayter
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译：在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到中断被延迟（例如，在提供给处理器之后）。中断可能会在超时到期时重新评估，并可能提供给另一个处理器。中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

6. 发明申请

US20120144172A1 Interrupt Distribution Scheme 有权
标题翻译：中断分配方案
公开(公告)号：US20120144172A1
公开(公告)日：2012-06-07
申请号：US12962146
申请日：2010-12-07
申请人： Josh P. de Cesare , Ruchi Wadhawan , Erik P. Machnicki , Mark D. Hayter
发明人： Josh P. de Cesare , Ruchi Wadhawan , Erik P. Machnicki , Mark D. Hayter
IPC分类号： G06F9/38
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译：在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到中断被延迟（例如，在提供给处理器之后）。中断可能会在超时到期时重新评估，并可能提供给另一个处理器。中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

7. 发明授权

US08458386B2 Atomic interrupt masking in an interrupt controller to prevent delivery of same interrupt vector for consecutive interrupt acknowledgements 有权
标题翻译：中断控制器中的原子中断屏蔽，以防止传递相同的中断向量用于连续的中断确认
公开(公告)号：US08458386B2
公开(公告)日：2013-06-04
申请号：US12962089
申请日：2010-12-07
申请人： Michael J. Smith , Josh P. de Cesare , Mark D. Hayter
发明人： Michael J. Smith , Josh P. de Cesare , Mark D. Hayter
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812 , G06F9/52
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译：在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到中断被延迟（例如，在提供给处理器之后）。中断可能会在超时到期时重新评估，并可能提供给另一个处理器。中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

8. 发明授权

US08443216B2 Hardware automatic performance state transitions in system on processor sleep and wake events 有权
公开(公告)号：US08443216B2
公开(公告)日：2013-05-14
申请号：US13590217
申请日：2012-08-21
申请人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
发明人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
IPC分类号： G06F1/00 , G06F1/26 , G06F3/038 , G06F3/00 , G09G3/18 , G11C5/14 , H04M1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

9. 发明申请

US20120260081A1 Adjusting Device Performance Based on Processing Profiles 有权
标题翻译：基于处理配置文件调整设备性能
公开(公告)号：US20120260081A1
公开(公告)日：2012-10-11
申请号：US13080280
申请日：2011-04-05
申请人： Josh P. de Cesare , Jonathan J. Andrews
发明人： Josh P. de Cesare , Jonathan J. Andrews
IPC分类号： G06F9/00
CPC分类号： G06F9/4893 , G06F1/3243 , Y02D10/152 , Y02D10/24
摘要： Adjusting processor performance based on processing profiles. The method may determine that a process has entered a processing state after an idle state. In response to entering the processing state the processing time of the processor may be monitored. In response to the processing time exceeding a first threshold of time, the performance of the processor may be increased from a first level to a second level. In response to the processing time exceeding a second threshold time, the performance of the processor may be decreased from the second level to a third level.
摘要翻译：基于处理配置文件调整处理器性能。该方法可以确定在空闲状态之后进程已进入处理状态。响应于进入处理状态，可以监视处理器的处理时间。响应于处理时间超过第一时间阈值，处理器的性能可以从第一级增加到第二级。响应于处理时间超过第二阈值时间，处理器的性能可以从第二级降低到第三级。

10. 发明申请

US20130043917A1 HARDWARE CONTROLLED PLL SWITCHING 有权
标题翻译：硬件控制PLL开关
公开(公告)号：US20130043917A1
公开(公告)日：2013-02-21
申请号：US13211004
申请日：2011-08-16
申请人： Josh P. de Cesare , Jung Wook Cho , Toshinari Takayanagi
发明人： Josh P. de Cesare , Jung Wook Cho , Toshinari Takayanagi
IPC分类号： H03L7/07
CPC分类号： H03L7/07 , G06F1/10
摘要： A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL.
摘要翻译：一种用于在芯片上的系统（SOC）上有效管理多个PLL的系统和方法。 SOC包括耦合到软件接口的硬件锁相环（PLL）切换控制块。硬件PLL切换（HPS）控制块从软件接收PLL切换请求。该请求识别由SOC上的多个处理器核心的给定处理核心接收的给定核心时钟，并且指示所识别的核心时钟不再由当前PLL提供。请求指示包括搜索条件的给定搜索方法。 HPS控制块搜索满足这些搜索条件的目标PLL。响应于找到目标PLL，HPS控制块改变SOC的管芯上的时钟网络连接和参数。芯片上的这些更改会将识别的内核时钟与当前的PLL断开连接，并将所识别的内核时钟连接到目标PLL。

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