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1. 发明申请

US20140063925A1 PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS 审中-公开
标题翻译：并行编程多相变化记忆细胞
公开(公告)号：US20140063925A1
公开(公告)日：2014-03-06
申请号：US13434739
申请日：2012-03-29
申请人： Daniel J. Friedman , Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Daniel J. Friedman , Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0085 , G11C2013/0088 , G11C2013/0092 , G11C2213/79
摘要： Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.
摘要翻译：本发明的实施例提供一种包括多个相变存储单元，字线和多个位线的装置。每个相变存储单元耦合到相应的晶体管。每个晶体管耦合到字线。每个位线耦合到器件的相变存储器单元。该装置还包括编程电路，其被配置为通过选择性地将两级波形应用于该装置的字线和位线来将至少一个相变存储器单元编程到SET状态。在第一阶段中，分别在字线和位线处施加第一预定低电压和第一预定高电压。在第二级中，分别在字线和位线处施加具有降低幅度的第二预定高电压和预定电压。

2. 发明授权

US07847529B2 Dual loop linear voltage regulator with high frequency noise reduction 有权
标题翻译：具有高频降噪功能的双回路线性稳压器
公开(公告)号：US07847529B2
公开(公告)日：2010-12-07
申请号：US11847416
申请日：2007-08-30
申请人： Seongwon Kim
发明人： Seongwon Kim
IPC分类号： G05F1/59
CPC分类号： G05F1/467
摘要： A linear voltage regulator is provided. The linear voltage regulator includes a first circuit configured to receive the first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node. The linear voltage regulator further includes a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit. The second circuit is configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range. The second frequency range is greater than the first frequency range.
摘要翻译：提供线性稳压器。线性稳压器包括被配置为从电压源接收第一电压并且去除第一频率范围中的第一电压的频率分量以获得主输出节点处的输出电压的第一电路。线性电压调节器还包括具有电耦合到第一电路的主输出节点的第一和第二反相器的第二电路。第二电路被配置为接收输出电压并且在第二频率范围中去除输出电压的频率分量。第二个频率范围大于第一个频率范围。

3. 发明授权

US07795762B2 On-chip high frequency power supply noise sensor 失效
标题翻译：片上高频电源噪声传感器
公开(公告)号：US07795762B2
公开(公告)日：2010-09-14
申请号：US11832379
申请日：2007-08-01
申请人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
发明人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
IPC分类号： H03K17/82
CPC分类号： H02H9/046
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise can be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a manner that does not require calibration. Also, since the sensor requires only one power supply, it can be used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can be tuned to detect down to whatever frequency is needed.
摘要翻译：片上电源噪声传感器检测电源电压的高频超频和欠压。通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。通过比较这些电流，可以感测到非常高频率的电源噪声的幅度，并用于设置锁存器或添加到数字计数器。这具有以不需要校准的方式直接感测电源噪声的优点。此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。最后，它滤除电路设计人员不感兴趣的任何较低频率的噪声，并且可以将其调谐到需要的频率。

4. 发明申请

US20090034144A1 On-Chip High Frequency Power Supply Noise Sensor 失效
标题翻译：片上高频电源噪声传感器
公开(公告)号：US20090034144A1
公开(公告)日：2009-02-05
申请号：US11832379
申请日：2007-08-01
申请人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
发明人： Daniel M. Dreps , Seongwon Kim , Michael A. Sperling
IPC分类号： H02H9/06
CPC分类号： H02H9/046
摘要： The on-chip power supply noise sensor detects high frequency overshoots and undershoots of the power supply voltage. By creating two identical current sources and attaching a time constant circuit to only one, the high frequency transient behavior differs while the low frequency behavior is equivalent. By comparing these currents, the magnitude of very high frequency power supply noise cars be sensed and used to either set latches or add to a digital counter. This has the advantage of directly sensing the power supply noise in a matter that does not require calibration. Also, since the sensor requires only one power supply, it can he used anywhere on a chip. Finally, it filters out any lower frequency noise that is not interesting to the circuit designer and can he timed to detect down to whatever frequency is needed.
摘要翻译：片上电源噪声传感器检测电源电压的高频超频和欠压。通过产生两个相同的电流源并将时间常数电路连接到一个，高频瞬态行为在低频行为相当时不同。通过比较这些电流，将检测非常高频率的电源噪声汽车的大小，并将其用于设置锁存器或添加到数字计数器。这具有直接感测不需要校准的物质中的电源噪声的优点。此外，由于传感器只需要一个电源，所以它可以在芯片的任何地方使用。最后，它滤除电路设计人员不感兴趣的任何低频噪声，并且可以定时检测到任何需要的频率。

5. 发明授权

US07177775B2 Testable digital delay line 失效
公开(公告)号：US07177775B2
公开(公告)日：2007-02-13
申请号：US11117924
申请日：2005-04-29
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G06F3/02
CPC分类号： G01R31/31725 , H03K2005/00039 , H03K2005/00156
摘要： A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.

6. 发明授权

US06885700B1 Charge-based frequency measurement bist 失效
标题翻译：基于充电的频率测量单元
公开(公告)号：US06885700B1
公开(公告)日：2005-04-26
申请号：US09669487
申请日：2000-09-25
申请人： Seongwon Kim , Mani Soma
发明人： Seongwon Kim , Mani Soma
IPC分类号： G01R31/30 , G01R31/317 , H03L7/089 , H03L7/18 , H04B17/00 , H04B3/46 , H04Q1/20
CPC分类号： G01R31/3016 , G01R31/31716 , G01R31/31725 , G01R31/31727 , H03L7/0891 , H03L7/18
摘要： A charge-based frequency measurement BIST (CF-BIST) for clock circuits and oscillator circuits is described that requires no outside test stimulus and produces a digital test output. The CF-BIST technique performs structural and defect-oriented testing and uses existing blocks to save die area. The technique adds a multiplexer to the non-sensitive digital path. The system uses the existing VCO as the measuring device and divide-by-N as a frequency counter to reduce the area overhead. The described technique produces an efficient pass/fail evaluation, low-cost and practical implementation of on-chip BIST structure.
摘要翻译：描述了用于时钟电路和振荡器电路的基于充电的频率测量BIST（CF-BIST），其不需要外部测试刺激并产生数字测试输出。 CF-BIST技术执行结构和缺陷导向测试，并使用现有的块来节省模具面积。该技术将多路复用器添加到非敏感数字路径。该系统使用现有的VCO作为测量设备，并将N分频为频率计数器，以减少面积开销。所描述的技术产生了片上BIST结构的有效通过/失败评估，低成本和实用的实现。

7. 发明申请

US20050050419A1 Self-synchronizing pseudorandom bit sequence checker 有权
标题翻译：自同步伪随机比特序列检验器
公开(公告)号：US20050050419A1
公开(公告)日：2005-03-03
申请号：US10650222
申请日：2003-08-28
申请人： Mohit Kapur , Seongwon Kim
发明人： Mohit Kapur , Seongwon Kim
IPC分类号： G01R31/28 , H04L1/20 , H04L1/24
CPC分类号： H04L1/242
摘要： Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.
摘要翻译：提供了用于检查伪随机比特序列（PRBS）的准确性的自同步技术。被检查的PRBS可以由设备（例如，被测设备）响应于设备接收的PRBS（例如，从PRBS生成器）生成。在本发明的一个方面，PRBS检查技术包括以下步骤/操作。对于给定的时钟周期，检测到由设备产生的PRBS中存在错误位。错误位表示设备的PRBS输入与设备的PRBS输出之间的不匹配。然后，错误位的传播在后续的时钟周期被禁止。禁止步骤/操作可以用于避免针对设备的PRBS输出中的单个错误发生和/或屏蔽错误而计数多个错误。

8. 发明授权

US08812879B2 Processor voltage regulation 有权
标题翻译：处理器电压调节
公开(公告)号：US08812879B2
公开(公告)日：2014-08-19
申请号：US12650516
申请日：2009-12-30
申请人： Huajun Wen , Joshua D. Friedrich , Norman K. James , Seongwon Kim , John R. Ripley , Edmund J. Sprogis
发明人： Huajun Wen , Joshua D. Friedrich , Norman K. James , Seongwon Kim , John R. Ripley , Edmund J. Sprogis
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G05F1/56 , G06F1/26 , G06F1/3287 , Y02D10/171
摘要： A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.
摘要翻译：电压调节器模块（VRM）包括被配置为以第一电压耦合到第一衬底接口的第一接口。 VRM还包括被配置为以第二电压耦合到第一处理器接口的第二接口。第一调节器模块耦合到第一接口和第二接口。第一调节器模块被配置为在第一接口处接收电力，以将功率转换为第二电压，并且以第二电压将功率输送到第一处理器接口。向处理器提供电力的方法包括以第一电压从第一基板接口接收功率。接收的功率被调节以在第二电压下产生功率。将调节的功率提供给耦合到处理器的第一处理器接口处的处理器。处理器接口向处理器的多个逻辑组的逻辑组递送电力。

9. 发明申请

US20120084241A1 PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES 有权
标题翻译：在使用相位变化的同步设备的神经网络中生产依赖于时间的相对塑性
公开(公告)号：US20120084241A1
公开(公告)日：2012-04-05
申请号：US12895791
申请日：2010-09-30
申请人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/063
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
摘要翻译：本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

10. 发明授权

US07863918B2 Disposable built-in self-test devices, systems and methods for testing three dimensional integrated circuits 有权
标题翻译：一次性内置自检装置，三维集成电路测试系统和方法
公开(公告)号：US07863918B2
公开(公告)日：2011-01-04
申请号：US11939145
申请日：2007-11-13
申请人： Keith A. Jenkins , Seongwon Kim
发明人： Keith A. Jenkins , Seongwon Kim
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , H01L22/20 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit.
摘要翻译：用于对三维集成电路的集成电路层进行自检的装置和方法包括在具有待测试的第一电路的共同衬底上一体地形成一次性自检电路。第一电路形成三维集成电路结构的层。第一个电路使用自检电路的电路进行测试。通过从第一电路分离自检电路来去除自检电路。

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