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1. 发明授权

US08897062B2 Memory programming for a phase change memory cell 有权
标题翻译：相变存储单元的存储器编程
公开(公告)号：US08897062B2
公开(公告)日：2014-11-25
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00 , G11C13/00 , G11C29/02
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

2. 发明申请

US20130166826A1 SOLID-STATE DEVICE MANAGEMENT 审中-公开
标题翻译：固态设备管理
公开(公告)号：US20130166826A1
公开(公告)日：2013-06-27
申请号：US13619424
申请日：2012-09-14
申请人： Michele M. Franceschini , Ashish Jagmohan
发明人： Michele M. Franceschini , Ashish Jagmohan
IPC分类号： G06F12/00
CPC分类号： G06F3/0688 , G06F3/0601 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0652 , G06F12/0246 , G06F2212/7201 , G06F2212/7211
摘要： An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.
摘要翻译：一个实施例是用于在固态存储板上的固态存储设备上建立第一逻辑地址和第一物理地址之间的对应关系的方法。固态存储装置包括通过物理地址识别的多个物理存储器位置，并且由位于与固态存储板分离的主板上的软件模块建立。第一逻辑地址和第一物理地址之间的对应关系存储在固态存储设备上的位于固态存储板上的地址转换器模块可访问的位置。固态存储器件位于固态存储板上。基于先前建立的第一逻辑地址和第一物理地址之间的对应关系，地址转换器模块将第一逻辑地址转换为第一物理地址。

3. 发明授权

US08463985B2 Constrained coding to reduce floating gate coupling in non-volatile memories 失效
标题翻译：约束编码以减少非易失性存储器中的浮动栅极耦合
公开(公告)号：US08463985B2
公开(公告)日：2013-06-11
申请号：US12751197
申请日：2010-03-31
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G06F12/02 , H03M13/00
CPC分类号： G11C16/0483 , G06F12/0246 , G06F2212/7202 , G11C7/1006 , G11C16/10
摘要： Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword.
摘要翻译：约束编码以减少非易失性存储器中的浮动栅极耦合，包括用于存储数据的方法。该方法包括接收要写入闪速存储器件的写入数据，响应写入数据选择一个代码字，以及将该代码字写入闪存器件。选择码字以通过防止在码字中发生指定的符号模式来减少闪存器件中的浮动栅极耦合。

4. 发明授权

US08374040B2 Write bandwidth in a memory characterized by a variable write time 有权
标题翻译：将带宽写入以可变写入时间为特征的存储器中
公开(公告)号：US08374040B2
公开(公告)日：2013-02-12
申请号：US13034936
申请日：2011-02-25
申请人： John A. Bivens , Michele M. Franceschini , Luis A. Lastras-Montano
发明人： John A. Bivens , Michele M. Franceschini , Luis A. Lastras-Montano
IPC分类号： G11C7/00
CPC分类号： G11C7/1012 , G06F2213/0038 , G11C13/0004 , G11C13/0069 , G11C2013/008
摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.
摘要翻译：一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。

5. 发明申请

US20130016556A1 PLANAR PHASE- CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS 有权
标题翻译：平面相变记忆电池与并联电气
公开(公告)号：US20130016556A1
公开(公告)日：2013-01-17
申请号：US13619473
申请日：2012-09-14
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region.
摘要翻译：一种用于操作相变存储器的方法，包括初始化存储单元，所述存储单元包括：具有大于其宽度的长度的第一导电电极和与所述长度对准的轴线; 第二导电电极，其具有与第一导电电极的轴成一定角度的边缘; 绝缘体，其在所述第一导电电极的端部和所述第二导电电极的边缘之间提供间隔距离; 以及覆盖所述第一导电电极的主要部分和所述第二导电电极的至少一部分的相变材料。初始化存储单元包括在相变材料中形成第一非晶态材料区域。在第一无定形材料区域内形成活性结晶材料区域。通过在活性结晶材料区域内产生第二非晶态材料区域将信息存储在存储器单元中。

6. 发明申请

US20130013886A1 ADAPTIVE WEAR LEVELING VIA MONITORING THE PROPERTIES OF MEMORY REFERENCE STREAM 有权
标题翻译：通过监测记忆参考流的性质，自适应磨损
公开(公告)号：US20130013886A1
公开(公告)日：2013-01-10
申请号：US13619513
申请日：2012-09-14
申请人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/1052 , G06F2212/7201 , G06F2212/7211
摘要： Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.
摘要翻译：在有限寿命的存储器设备中的自适应写平均化，包括执行用于监视包括写入行地址的写入数据流的方法。检测写入数据流的属性，并响应于检测到的属性来调整写入调平过程。写入平均过程被应用于写入数据流以从写入地址生成物理地址。

7. 发明申请

US20130013860A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 有权
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20130013860A1
公开(公告)日：2013-01-10
申请号：US13619451
申请日：2012-09-14
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
摘要翻译：用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值存储器单元的指定状态到存储器单元的期望状态。第二期望值比第一期望值更接近写入性能特性的期望值。区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

8. 发明授权

US08352839B2 Encoding data into constrained memory 失效
标题翻译：将数据编码到受限内存中
公开(公告)号：US08352839B2
公开(公告)日：2013-01-08
申请号：US12814142
申请日：2010-06-11
申请人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： H03M13/00
CPC分类号： G11C13/0004 , G11C7/1006 , G11C13/00 , G11C13/0069
摘要： Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word.
摘要翻译：使用用于写入数据的方法将数据编码到约束存储器中，该方法包括接收要编码的写入数据到写入字中，接收与写入字相关联的符号值的约束，将写入数据编码到写入字中，以及将写入字写入一个记忆编码包括：在第一尺寸的第一场中表示作为第一线性系统的写入数据和约束; 在第二尺寸的第二场中将第一线性系统嵌入第二线性系统中，第二尺寸大于第一尺寸; 求解第二个场中的第二个线性系统，得到解决方案; 并且将解决方案折叠到第一场中，导致写入字，写入字满足与写入字相关联的符号值的约束。

9. 发明申请

US20120290898A1 ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的自适应耐久编码
公开(公告)号：US20120290898A1
公开(公告)日：2012-11-15
申请号：US13556275
申请日：2012-07-24
申请人： MIchele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： MIchele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data.
摘要翻译：适应性耐力编码包括用于访问存储器的方法，包括从存储器地址检索码字。将码字乘以元数据矩阵以恢复码字的元数据。元数据包括数据位置规范。代码字中的数据是响应于元数据而被识别的，数据被输出为读取数据。

10. 发明申请

US20120287714A1 INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS 有权
标题翻译：增加容量异质存储元素
公开(公告)号：US20120287714A1
公开(公告)日：2012-11-15
申请号：US13557298
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00 , G11C11/00 , G11C16/04
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.
摘要翻译：在异构存储元件中提供增加的容量，包括从存储器读取的方法。该方法包括从存储器单元块接收读取字，其中存储器单元的物理特性支持不同数据级的集合。读取的字被分成两个或更多个虚拟读取向量。对于每个虚拟读取向量，识别用于生成虚拟读取向量的码本，并生成部分读取数据向量。生成包括将虚拟读取向量乘以代表码本的矩阵。将部分读取数据矢量组合成读取消息，并输出读出的消息。

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