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1. 发明授权

US08656109B2 Systems and methods for background destaging storage tracks 失效
标题翻译：后台存储轨道的系统和方法
公开(公告)号：US08656109B2
公开(公告)日：2014-02-18
申请号：US12965141
申请日：2010-12-10
申请人： Brent C. Beardsley , Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , Sonny E. Williams
发明人： Brent C. Beardsley , Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , Sonny E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0831 , G06F12/0848 , G06F12/0866 , G06F12/0868 , G06F12/12 , G06F12/128 , G06F2212/1041 , G06F2212/282 , G06F2212/313 , G06F2212/314 , G06F2212/604 , G06F2212/621
摘要： A system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.
摘要翻译：一种系统包括配置成存储多个存储轨道并被配置为耦合到一个或多个主机的写入高速缓存以及耦合到写入高速缓存的处理器。处理器包括当由处理器执行时使处理器执行下面的方法的代码。一种方法包括：监控来自主机的写入高速缓存，以及基于监视来自主机的写入操作的写入高速缓存来确定主机是否是空闲的。如果主机是空闲的并且如果一个或多个主机不空闲，则不会从写高速缓存中将存储轨道从写高速缓存中移出。还提供了包括用于执行上述方法的计算机程序产品的物理计算机存储介质。

2. 发明授权

US08443141B2 Intelligent write caching for sequential tracks 有权
标题翻译：用于顺序轨道的智能写缓存
公开(公告)号：US08443141B2
公开(公告)日：2013-05-14
申请号：US12894017
申请日：2010-09-29
申请人： Brent C. Beardsley , Michael T. Benhase , Lokesh M. Gupta , Joseph S. Hyde, II , Sonny E. Williams
发明人： Brent C. Beardsley , Michael T. Benhase , Lokesh M. Gupta , Joseph S. Hyde, II , Sonny E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0804 , G06F12/0868
摘要： Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation.
摘要翻译：用于顺序轨道的写缓存由用于将数据从非易失性存储（NVS）降级到存储单元的计算存储环境中的处理器设备执行。如果确定第一轨道是顺序的，并且较早的轨道也被确定为顺序的，则与较早轨道相关联的时间位被清除以允许对先前轨道的数据进行排水。如果确定修改的高速缓存中的多个步幅之一中的多个附加轨道之一的时间位未被设置，则选择与所述多个附加轨道中的一个相关联的步幅用于码头操作。如果NVS超过预定的存储阈值，则选择多个步骤中的预定的一个步骤用于排水操作。

3. 发明申请

US20120151148A1 SYSTEMS AND METHODS FOR BACKGROUND DESTAGING STORAGE TRACKS 失效
标题翻译：背景技术存储轨迹的系统和方法
公开(公告)号：US20120151148A1
公开(公告)日：2012-06-14
申请号：US12965141
申请日：2010-12-10
申请人： Brent C. BEARDSLEY , Michael T. BENHASE , Binny S. GILL , Lokesh M. GUPTA , Sonny E. WILLIAMS
发明人： Brent C. BEARDSLEY , Michael T. BENHASE , Binny S. GILL , Lokesh M. GUPTA , Sonny E. WILLIAMS
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0831 , G06F12/0848 , G06F12/0866 , G06F12/0868 , G06F12/12 , G06F12/128 , G06F2212/1041 , G06F2212/282 , G06F2212/313 , G06F2212/314 , G06F2212/604 , G06F2212/621
摘要： Systems and methods for background destaging storage tracks from cache when one or more hosts are idle are provided. One system includes a write cache configured to store a plurality of storage tracks and configured to be coupled to one or more hosts, and a processor coupled to the write cache. The processor includes code that, when executed by the processor, causes the processor to perform the method below. One method includes monitoring the write cache for write operations from the host(s) and determining if the host(s) is/are idle based on monitoring the write cache for write operations from the host(s). The storage tracks are destaged from the write cache if the host(s) is/are idle and are not destaged from the write cache if one or more of the hosts is/are not idle. Also provided are physical computer storage mediums including a computer program product for performing the above method.
摘要翻译：提供了当一个或多个主机空闲时，用于从高速缓存中进行后台存储轨道的后台运行的系统和方法。一个系统包括被配置为存储多个存储轨道并且被配置为耦合到一个或多个主机的写入高速缓存以及耦合到写入高速缓存的处理器。处理器包括当由处理器执行时使处理器执行下面的方法的代码。一种方法包括：监控来自主机的写入高速缓存，以及基于监视来自主机的写入操作的写入高速缓存来确定主机是否是空闲的。如果主机是空闲的并且如果一个或多个主机不空闲，则不会从写高速缓存中将存储轨道从写高速缓存中移出。还提供了包括用于执行上述方法的计算机程序产品的物理计算机存储介质。

4. 发明授权

US07676616B2 Method, apparatus and program storage device for providing asynchronous status messaging in a data storage system 有权
标题翻译：用于在数据存储系统中提供异步状态消息的方法，装置和程序存储装置
公开(公告)号：US07676616B2
公开(公告)日：2010-03-09
申请号：US11852125
申请日：2007-09-07
申请人： Brent C. Beardsley , Minh-Ngoc Le Huynh , William F. Micka , Satish Chandra Penmetsa , Richard A. Schaeffer , Kaukab Uddin
发明人： Brent C. Beardsley , Minh-Ngoc Le Huynh , William F. Micka , Satish Chandra Penmetsa , Richard A. Schaeffer , Kaukab Uddin
IPC分类号： G06F13/42 , G06F3/00
CPC分类号： G06F13/385 , G06F13/42 , G06F2213/0036
摘要： A method, apparatus and program storage device for providing asynchronous status messaging in a data storage system Asynchronous events are returned from a target to an initiator in response to a Read Message from the initiator. The return status message may or may not be associated with a previously given command or Logical Unit (LUN).
摘要翻译：一种用于在数据存储系统中提供异步状态消息的方法，装置和程序存储装置响应于来自发起者的读取消息，异步事件从目标返回到发起者。返回状态消息可以或可以不与先前给出的命令或逻辑单元（LUN）相关联。

5. 发明授权

US06298398B1 Method to provide checking on data transferred through fibre channel adapter cards 有权
标题翻译：用于保护在多个信息单元中在网络中发送的数据块的方法
公开(公告)号：US06298398B1
公开(公告)日：2001-10-02
申请号：US09433772
申请日：1999-11-03
申请人： Joseph C. Elliott , Daniel F. Casper , Louis W. Ricci , Brent C. Beardsley , Catherine C. Huang
发明人： Joseph C. Elliott , Daniel F. Casper , Louis W. Ricci , Brent C. Beardsley , Catherine C. Huang
IPC分类号： G06F1110
CPC分类号： G06F13/122
摘要： The present invention provides checking on information units sent and received as packets over fiber channel networks by providing check bits on the header information and separate check bits on the data.
摘要翻译：本发明通过在标题信息上提供校验位和在数据上分开校验位来提供通过光纤通道网络发送和接收为分组的信息单元的检查。

6. 发明授权

US5461720A System for increasing the efficiency of communications between controller and plurality of host computers by prohibiting retransmission of the same message for predetermined period of time 失效
标题翻译：用于通过禁止在预定时间段内重传相同消息来提高控制器与多台主机之间的通信效率的系统
公开(公告)号：US5461720A
公开(公告)日：1995-10-24
申请号：US949671
申请日：1992-09-23
申请人： Brent C. Beardsley , Adalberto G. Yanes
发明人： Brent C. Beardsley , Adalberto G. Yanes
IPC分类号： G06F13/16 , G06F15/02
CPC分类号： G06F13/161
摘要： A method and system for enhancing the efficiency of communication between multiple host computers and a storage system controller via multiple communication channels. After detecting a transmission of a specific message from the storage system controller to a selected host computer, channel data bits corresponding to that particular communication channel are set within preliminary control words which are stored in temporary storage locations. A timer circuit is coupled to the temporary storage locations and periodically resets the channel data bits. A final control word is then calculated by combining the channel data bits from all of the preliminary control words. A control circuit is then utilized to prohibit the retransmission of the specific message from the storage system controller to the selected host computer for a predetermined minimum period of time in response to the state of the channel data bits within the final control word. Communication efficiency is increased by eliminating unnecessary transmissions of a specific message.
摘要翻译：一种用于通过多个通信信道增强多个主机与存储系统控制器之间的通信效率的方法和系统。在检测到来自存储系统控制器的特定消息到所选择的主计算机的传输之后，将对应于该特定通信信道的通道数据位设置在存储在临时存储位置的初步控制字中。定时器电路耦合到临时存储位置，并周期性地复位通道数据位。然后通过组合来自所有初步控制字的通道数据位来计算最终控制字。然后，响应于最终控制字内的通道数据位的状态，控制电路用于禁止将特定消息从存储系统控制器重传到所选择的主计算机预定的最小时间段。通过消除特定消息的不必要的传输来增加通信效率。

7. 发明授权

US5446872A Method for error recovery in a non-synchronous control unit 失效
标题翻译：非同步控制单元中的错误恢复方法
公开(公告)号：US5446872A
公开(公告)日：1995-08-29
申请号：US082349
申请日：1993-06-23
申请人： Kathryn J. Ayres , Brent C. Beardsley , Keith A. Bello , Michael T. Benhase , Donald M. Nordahl , Alfred G. Torre , Bao T. Trieu , Linda D. VanPatten
发明人： Kathryn J. Ayres , Brent C. Beardsley , Keith A. Bello , Michael T. Benhase , Donald M. Nordahl , Alfred G. Torre , Bao T. Trieu , Linda D. VanPatten
IPC分类号： G06F11/00 , G06F3/06 , G06F5/14 , G06F11/36 , G06F13/00 , G06F13/38
CPC分类号： G06F11/366
摘要： An error recovery process for a non-synchronous DASD control unit. A channel process within the control unit is able to operate on different fields from a device process within the control unit. Independent errors may be sensed by each process. The error recovery process provides for restarting only the trailing process and deferring handling of the error sensed by the leading process, whenever possible.
摘要翻译：非同步DASD控制单元的错误恢复过程。控制单元内的通道过程能够在与控制单元内的设备过程不同的领域操作。每个过程可能会感知到独立的错误。错误恢复过程仅在可能的情况下重新启动尾随进程并推迟处理由主流进程感测到的错误。

8. 发明授权

US08661202B2 Systems and methods for destaging storage tracks from cache 有权
标题翻译：从缓存中降级存储轨道的系统和方法
公开(公告)号：US08661202B2
公开(公告)日：2014-02-25
申请号：US12965174
申请日：2010-12-10
申请人： Brent C. Beardsley , Michael T. Benhase , Lokesh M. Gupta , Sonny E. Williams
发明人： Brent C. Beardsley , Michael T. Benhase , Lokesh M. Gupta , Sonny E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F12/0804
摘要： A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count. Also provided are physical computer storage mediums including a computer program product for performing the above method.
摘要翻译：系统包括高速缓存和耦合到高速缓存的处理器。高速缓存将数据存储在多个存储轨道中，并且每个存储轨道包括相关联的多位计数器。处理器配置为执行以下方法。一种方法包括：在每次处理器向相应的存储轨道写入时，将数据写入多个存储轨道，并将每个相应存储轨道上的多位计数器递增预定量。该方法还包括在多个扫描周期中的每一个扫描每个存储轨道，递减每个多位计数器每个扫描周期，以及降级包括零计数的每个存储轨道。还提供了包括用于执行上述方法的计算机程序产品的物理计算机存储介质。

9. 发明授权

US08639888B2 Systems and methods for managing cache destage scan times 有权
标题翻译：用于管理缓存目的地扫描时间的系统和方法
公开(公告)号：US08639888B2
公开(公告)日：2014-01-28
申请号：US12965131
申请日：2010-12-10
申请人： Brent C. Beardsley , Michael T. Benhase , Lokesh M. Gupta , Sonny E. Williams
发明人： Brent C. Beardsley , Michael T. Benhase , Lokesh M. Gupta , Sonny E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F12/0859 , G06F12/0866
摘要： A system includes a cache and a processor. The processor is configured to utilize a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilize a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time. One method includes utilizing a first thread to continually determine a desired scan time for scanning the plurality of storage tracks in the cache and utilizing a second thread to continually control an actual scan time of the plurality of storage tracks in the cache based on the continually determined desired scan time.
摘要翻译：系统包括缓存和处理器。处理器被配置为利用第一线程来连续地确定用于扫描高速缓存中的多个存储轨道的期望的扫描时间，并且利用第二线程基于所述缓存器来连续地控制多个存储轨道的实际扫描时间持续确定所需的扫描时间。一种方法包括利用第一线程来连续地确定用于扫描高速缓存中的多个存储轨道的期望的扫描时间，并且利用第二线程基于连续地确定的高速缓存中的多个存储轨道的实际扫描时间所需的扫描时间。

10. 发明授权

US08566535B2 Systems and methods for destaging storage tracks from cache 失效
标题翻译：从缓存中降级存储轨道的系统和方法
公开(公告)号：US08566535B2
公开(公告)日：2013-10-22
申请号：US13493802
申请日：2012-06-11
申请人： Brent C. Beardsley , Michael T. Benhase , Lokesh M. Gupta , Sonny E. Williams
发明人： Brent C. Beardsley , Michael T. Benhase , Lokesh M. Gupta , Sonny E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F12/0804
摘要： A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count.
摘要翻译：系统包括高速缓存和耦合到高速缓存的处理器。高速缓存将数据存储在多个存储轨道中，并且每个存储轨道包括相关联的多位计数器。处理器配置为执行以下方法。一种方法包括：在每次处理器向相应的存储轨道写入时，将数据写入多个存储轨道，并将每个相应存储轨道上的多位计数器递增预定量。该方法还包括在多个扫描周期中的每一个扫描每个存储轨道，递减每个多位计数器每个扫描周期，以及降级包括零计数的每个存储轨道。

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