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1. 发明授权

US07984222B2 Systems for providing performance monitoring in a memory system 有权
标题翻译：用于在存储器系统中提供性能监视的系统
公开(公告)号：US07984222B2
公开(公告)日：2011-07-19
申请号：US12352990
申请日：2009-01-13
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
IPC分类号： G06F13/14 , G06F13/24 , G06F12/06 , G06F13/00
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译：用于在存储器系统中提供性能监视的系统。存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。存储器控制器接收和响应存储器访问请求。存储器总线与存储器控制器通信。存储器集线器设备与存储器总线通信。存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。存储器集线器设备还包括用于与存储器件通信的存储器设备接口。存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。

2. 发明授权

US07437622B2 Implementation-efficient multiple-counter value hardware performance counter 失效
标题翻译：实现高效的多计数器硬件性能计数器
公开(公告)号：US07437622B2
公开(公告)日：2008-10-14
申请号：US11738497
申请日：2007-04-22
申请人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
发明人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.
摘要翻译：公开了一种实现高效的多计数器硬件性能计数器。一个实施例的硬件计数器包括存储器阵列和硬件递增器。阵列存储可由至少基于计数器值对应的事件数构成的索引可索引的计数器值。索引可以被构造为二进制数表示事件数量的位数的连接，以及二进制表示事件的限定符的数目的位数。增量器从数组中读取计数器值，增加计数器值，并将生成的计数器值写入数组。阵列可以被划分为存储有计数器值的存储体，其中每个存储体具有加法器的单独实例。每个银行可能有一个单独的索引实例，仅索引存储在银行中的那些计数器。

3. 发明授权

US06848026B2 Caching memory contents into cache partitions based on memory locations 失效
标题翻译：基于内存位置将内存缓存缓存分区缓存
公开(公告)号：US06848026B2
公开(公告)日：2005-01-25
申请号：US10010788
申请日：2001-11-09
申请人： Donald R. DeSota , Adrian C. Moga , Carl E. Love , Russell M. Clapp
发明人： Donald R. DeSota , Adrian C. Moga , Carl E. Love , Russell M. Clapp
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0864 , G06F12/0848
摘要： Caching memory contents into cache partitions based on their locations is disclosed. A location of a line of memory to be cached in a cache is determined. The cache is partitioned into a number of cache sections. The section for the line of memory is determined based on the location of the line of memory as applied against a memory line location-dependent allocation policy. The line of memory is then stored in the section of the cache determined.
摘要翻译：公开了将存储器内容基于其位置缓存到高速缓存分区中。确定要缓存在高速缓存中的一行内存的位置。缓存被分割成多个高速缓存部分。存储器行的部分基于针对存储器线路位置相关分配策略应用的存储器行的位置来确定。然后将存储器行存储在所确定的缓存部分中。

4. 发明申请

US20090119466A1 SYSTEMS FOR PROVIDING PERFORMANCE MONITORING IN A MEMORY SYSTEM 有权
标题翻译：用于在存储系统中提供性能监控的系统
公开(公告)号：US20090119466A1
公开(公告)日：2009-05-07
申请号：US12352990
申请日：2009-01-13
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译：用于在存储器系统中提供性能监视的系统。存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。存储器控制器接收和响应存储器访问请求。存储器总线与存储器控制器通信。存储器集线器设备与存储器总线通信。存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。存储器集线器设备还包括用于与存储器件通信的存储器设备接口。存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。

5. 发明授权

US07493439B2 Systems and methods for providing performance monitoring in a memory system 有权
标题翻译：在存储系统中提供性能监控的系统和方法
公开(公告)号：US07493439B2
公开(公告)日：2009-02-17
申请号：US11461567
申请日：2006-08-01
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
IPC分类号： G06F13/14 , G06F13/24 , G06F12/00
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译：在存储系统中提供性能监控的系统和方法。实施例包括用于存储和检索用于处理系统的数据的存储器系统。存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。存储器控制器接收和响应存储器访问请求。存储器总线与存储器控制器通信。存储器集线器设备与存储器总线通信。存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。存储器集线器设备还包括用于与存储器件通信的存储器设备接口。存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。

6. 发明申请

US20080263263A1 Implementation-efficient multiple-counter value hardware performance counter 有权
公开(公告)号：US20080263263A1
公开(公告)日：2008-10-23
申请号：US12164094
申请日：2008-06-29
申请人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
发明人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
IPC分类号： G06F12/00
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.

7. 发明申请

US20080034148A1 SYSTEMS AND METHODS FOR PROVIDING PERFORMANCE MONITORING IN A MEMORY SYSTEM 有权
标题翻译：用于在存储器系统中提供性能监视的系统和方法
公开(公告)号：US20080034148A1
公开(公告)日：2008-02-07
申请号：US11461567
申请日：2006-08-01
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
IPC分类号： G06F12/02 , G06F13/28
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译：在存储系统中提供性能监控的系统和方法。实施例包括用于存储和检索用于处理系统的数据的存储器系统。存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。存储器控制器接收和响应存储器访问请求。存储器总线与存储器控制器通信。存储器集线器设备与存储器总线通信。存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。存储器集线器设备还包括用于与存储器件通信的存储器设备接口。存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。

8. 发明授权

US07861126B2 Implementation-efficient multiple-counter value hardware performance counter 有权
标题翻译：实现高效的多计数器硬件性能计数器
公开(公告)号：US07861126B2
公开(公告)日：2010-12-28
申请号：US12164094
申请日：2008-06-29
申请人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
发明人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.
摘要翻译：公开了一种实现高效的多计数器硬件性能计数器。一个实施例的硬件计数器包括存储器阵列和硬件递增器。阵列存储可由至少基于计数器值对应的事件数构成的索引可索引的计数器值。索引可以被构造为二进制数表示事件数量的位数的连接，以及二进制表示事件的限定符的数目的位数。增量器从数组中读取计数器值，增加计数器值，并将生成的计数器值写入数组。阵列可以被划分为存储有计数器值的存储体，其中每个存储体具有加法器的单独实例。每个银行可能有一个单独的索引实例，仅索引存储在银行中的那些计数器。

9. 发明授权

US07272754B2 Implementation-efficient multiple-counter value hardware performance counter 有权
公开(公告)号：US07272754B2
公开(公告)日：2007-09-18
申请号：US10672758
申请日：2003-09-27
申请人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
发明人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.

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