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1. 发明授权

US07954021B2 Solid state drive with flash sparing 有权
标题翻译：带闪光灯的固态硬盘驱动器
公开(公告)号：US07954021B2
公开(公告)日：2011-05-31
申请号：US12604614
申请日：2009-10-23
申请人： Gregg S. Lucas , Gary A. Tressler , Dustin J. Vanstee , Andrew D. Walls
发明人： Gregg S. Lucas , Gary A. Tressler , Dustin J. Vanstee , Andrew D. Walls
IPC分类号： G11C29/00
CPC分类号： G06F11/2094 , G06F11/073 , G06F11/076 , G06F11/1048 , G06F11/1662
摘要： A method for flash sparing on a solid state drive (SSD) includes detecting a failure from a primary memory device; determining if a failure threshold for the primary memory device has been reached; and, in the event the failure threshold for the primary memory device has been reached: quiescing the SSD; and updating an entry in a sparing map table to replace the primary memory device with a spare memory device.
摘要翻译：用于在固态驱动器（SSD）上闪存保存的方法包括从主存储器件检测故障; 确定是否已经达到主存储器件的故障阈值; 并且在主存储器件的故障阈值已达到的情况下：静止SSD; 以及更新备用映射表中的条目以用备用存储器设备替换主存储器设备。

2. 发明申请

US20090119466A1 SYSTEMS FOR PROVIDING PERFORMANCE MONITORING IN A MEMORY SYSTEM 有权
标题翻译：用于在存储系统中提供性能监控的系统
公开(公告)号：US20090119466A1
公开(公告)日：2009-05-07
申请号：US12352990
申请日：2009-01-13
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译：用于在存储器系统中提供性能监视的系统。存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。存储器控制器接收和响应存储器访问请求。存储器总线与存储器控制器通信。存储器集线器设备与存储器总线通信。存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。存储器集线器设备还包括用于与存储器件通信的存储器设备接口。存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。

3. 发明授权

US07493439B2 Systems and methods for providing performance monitoring in a memory system 有权
标题翻译：在存储系统中提供性能监控的系统和方法
公开(公告)号：US07493439B2
公开(公告)日：2009-02-17
申请号：US11461567
申请日：2006-08-01
申请人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
发明人： Kevin C. Gower , Carl E. Love , Dustin J. VanStee
IPC分类号： G06F13/14 , G06F13/24 , G06F12/00
CPC分类号： G06F13/1668 , G06F11/3419 , G06F11/3476 , G06F11/349 , G06F2201/86 , G06F2201/88 , Y02D10/14 , Y02D10/34
摘要： Systems and methods for providing performance monitoring in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
摘要翻译：在存储系统中提供性能监控的系统和方法。实施例包括用于存储和检索用于处理系统的数据的存储器系统。存储器系统包括存储器控制器，多个存储器件，存储器总线和存储器集线器设备。存储器控制器接收和响应存储器访问请求。存储器总线与存储器控制器通信。存储器集线器设备与存储器总线通信。存储器集线器设备包括用于经由存储器总线在存储器集线器设备和存储器控制器之间传送地址，控制和数据信息中的一个或多个的存储器接口。存储器集线器设备还包括用于与存储器件通信的存储器设备接口。存储器集线器设备还包括性能监视器，用于在系统操作期间在定义的间隔上监视和报告存储器总线利用率，存储器件利用率和性能特性中的一个或多个。

4. 发明申请

US20080183977A1 SYSTEMS AND METHODS FOR PROVIDING A DYNAMIC MEMORY BANK PAGE POLICY 失效
标题翻译：提供动态记忆库银行政策的系统和方法
公开(公告)号：US20080183977A1
公开(公告)日：2008-07-31
申请号：US11668093
申请日：2007-01-29
申请人： Kevin C. Gower , Dustin J. VanStee
发明人： Kevin C. Gower , Dustin J. VanStee
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F12/0215 , G06F13/161 , G06F13/1684
摘要： Systems and methods for providing a dynamic memory buffer bank policy. Embodiments include a hub device for selecting a bank page policy. The hub device includes an input command stream interface and a bank page policy module. The input command stream interface detects commands from a memory controller that are directed to one or more memory devices that are connected to the hub device. The bank page policy module independently analyzes the commands to determine access patterns to the memory devices and for dynamically selecting between an open bank page policy and a closed bank page policy for the memory devices based on the analysis.
摘要翻译：提供动态内存缓冲区银行策略的系统和方法。实施例包括用于选择银行页面策略的集线器设备。集线器设备包括输入命令流接口和银行页策略模块。输入命令流接口检测来自存储器控制器的命令，其被定向到连接到集线器设备的一个或多个存储器设备。银行页面策略模块独立地分析用于确定对存储器设备的访问模式的命令，并且基于分析来动态地在存储设备的开放银行页面策略和封闭的银行页面策略之间进行选择。

5. 发明授权

US08832506B2 Bit error rate based wear leveling for solid state drive memory 有权
标题翻译：固态硬盘存储器的基于误码率的磨损均衡
公开(公告)号：US08832506B2
公开(公告)日：2014-09-09
申请号：US13355050
申请日：2012-01-20
申请人： Thomas J. Griffin , Dustin J. Vanstee
发明人： Thomas J. Griffin , Dustin J. Vanstee
IPC分类号： G06F11/00 , G11C29/00 , G01R31/28 , H03M13/00 , G11C16/34 , H04L1/20 , G06F11/16 , G01R31/317 , G11C11/406 , G11C16/16 , G11C29/50 , G11C29/42 , G11C16/14 , G11C16/10 , G06F11/10
CPC分类号： G01R31/3171 , G06F11/008 , G06F11/076 , G06F11/1048 , G06F11/1068 , G06F11/16 , G11C11/406 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/3468 , G11C16/3495 , G11C29/42 , G11C29/50 , H04L1/203
摘要： According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
摘要翻译：根据示例性实施例，提供了一种用于SSD中的基于BER的磨损均衡的系统，方法和计算机程序产品。确定SSD中的块的块级BER值。块的调整PE周期计数根据块级BER值递增或递减。然后，根据调整后的PE循环次数，在SSD中进行磨损均衡。

6. 发明授权

US08015426B2 System and method for providing voltage power gating 失效
标题翻译：提供电压门控的系统和方法
公开(公告)号：US08015426B2
公开(公告)日：2011-09-06
申请号：US12056566
申请日：2008-03-27
申请人： Dustin J. VanStee , Thomas J. Griffin , Leonard M. Greenberg
发明人： Dustin J. VanStee , Thomas J. Griffin , Leonard M. Greenberg
IPC分类号： G06F1/32
CPC分类号： G11C5/14 , G11C5/04
摘要： A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.
摘要翻译：一种提供电压门控的系统和方法。该系统包括用于提供电压电源门控的装置。该装置包括逻辑电路，用于接收与逻辑电路相关联的控制信号和选择器的机构。控制信号指示逻辑电路的活动状态或空闲状态。响应于指示活动状态的控制信号，该选择器使能逻辑电路的电源。响应于指示空闲状态的控制信号，选择器还禁用逻辑电路的电源。因此，当电源处于空闲状态时，电源在设备上的逻辑电路中被动态地消除。

7. 发明申请

US20110099419A1 SOLID STATE DRIVE WITH FLASH SPARING 有权
标题翻译：固态驱动与闪存
公开(公告)号：US20110099419A1
公开(公告)日：2011-04-28
申请号：US12604614
申请日：2009-10-23
申请人： Gregg S. Lucas , Gary A. Tressler , Dustin J. Vanstee , Andrew D. Walls
发明人： Gregg S. Lucas , Gary A. Tressler , Dustin J. Vanstee , Andrew D. Walls
IPC分类号： G06F11/16 , G06F12/00 , G06F12/02 , G06F11/00
CPC分类号： G06F11/2094 , G06F11/073 , G06F11/076 , G06F11/1048 , G06F11/1662
摘要： A method for flash sparing on a solid state drive (SSD) includes detecting a failure from a primary memory device; determining if a failure threshold for the primary memory device has been reached; and, in the event the failure threshold for the primary memory device has been reached: quiescing the SSD; and updating an entry in a sparing map table to replace the primary memory device with a spare memory device.
摘要翻译：用于在固态驱动器（SSD）上闪存保存的方法包括从主存储器件检测故障; 确定是否已经达到主存储器件的故障阈值; 并且在主存储器件的故障阈值已达到的情况下：静止SSD; 以及更新备用映射表中的条目以用备用存储器设备替换主存储器设备。

8. 发明授权

US07669086B2 Systems and methods for providing collision detection in a memory system 有权
标题翻译：用于在存储器系统中提供碰撞检测的系统和方法
公开(公告)号：US07669086B2
公开(公告)日：2010-02-23
申请号：US11461933
申请日：2006-08-02
申请人： Kevin C. Gower , Thomas J. Griffin , Dustin J. VanStee
发明人： Kevin C. Gower , Thomas J. Griffin , Dustin J. VanStee
IPC分类号： G06F11/00
CPC分类号： G06F13/4239 , G06F9/52
摘要： Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.
摘要翻译：用于在包括用于存储和检索用于处理系统的数据的存储器系统的存储器系统中提供冲突检测的系统和方法。存储器系统包括用于监视用于检测资源调度冲突的一个或多个存储器资源的资源调度冲突逻辑。存储器系统还包括用于响应于检测到一个或多个存储器资源上的资源调度冲突而产生错误信号的错误报告逻辑。

9. 发明申请

US20080183903A1 SYSTEMS AND METHODS FOR PROVIDING DYNAMIC MEMORY PRE-FETCH 有权
标题翻译：提供动态存储器预充电器的系统和方法
公开(公告)号：US20080183903A1
公开(公告)日：2008-07-31
申请号：US11668088
申请日：2007-01-29
申请人： Dustin J. VanStee , Kevin C. Gower
发明人： Dustin J. VanStee , Kevin C. Gower
IPC分类号： G06F3/00
CPC分类号： G06F13/161
摘要： Systems and methods for providing dynamic memory pre-fetch. Embodiments include a hub device including an input command stream interface and an adaptive pre-fetch logical unit (APLU). The input command stream interface detects commands from a memory controller directed to one or more memory devices that are connected to the hub device. The APLU independently analyzes the commands to determine access patterns to the memory devices. The APLU also dynamically selects between enabling a pre-fetch function and disabling the pre-fetch function for the memory devices based on the results of the analysis.
摘要翻译：提供动态内存预取的系统和方法。实施例包括包括输入命令流接口和自适应预取逻辑单元（APLU）的集线器设备。输入命令流接口检测来自指向连接到集线器设备的一个或多个存储器设备的存储器控制器的命令。 APLU独立分析命令以确定存储器件的访问模式。 APLU还可以根据分析结果动态选择启用预取功能和禁用存储设备的预取功能。

10. 发明授权

US07181659B2 Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability 失效
标题翻译：内存自检引擎装置和方法，具有故障触发和每种负载能力的多种模式
公开(公告)号：US07181659B2
公开(公告)日：2007-02-20
申请号：US11055195
申请日：2005-02-10
申请人： Elianne A. Bravo , Kenneth Y. Chan , Kevin C. Gower , Dustin J. VanStee
发明人： Elianne A. Bravo , Kenneth Y. Chan , Kevin C. Gower , Dustin J. VanStee
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C11/401
摘要： A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.
摘要翻译：用于测试动态随机存取存储器（DRAM）阵列的存储器内置自检（MBIST）装置和方法，所述DRAM阵列与包括接口逻辑和主线芯片逻辑的存储器接口装置通信。 MBIST装置包括有限状态机，其包括用于递增待测数据和地址的命令发生器和逻辑，以及与有限状态机通信的命令调度器。命令调度器包括用于动态地利用DRAM时序参数将命令间隔到存储器的资源分配逻辑。 MBIST设备还包括存储MBIST测试的分测验的测试存储器。每个分测验提供完整的配置地址范围。 MBIST装置还包括与测试存储器和有限状态机通信的子测试指针。有限状态机通过子测验指针实现每个子测验的子测序。

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