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1. 发明申请

US20130117766A1 Fabric-Backplane Enterprise Servers with Pluggable I/O Sub-System 有权
标题翻译：具有可插拔I / O子系统的布线背板企业服务器
公开(公告)号：US20130117766A1
公开(公告)日：2013-05-09
申请号：US11736355
申请日：2007-04-17
申请人： Daniel H. Bax , William Jackson Bibb, JR. , Russell M. Clapp , Tom Gourley , Geoffrey H. Hanson , Allen Hirashiki , Thomas Dean Lovett , Sharad Mehrotra , Shyam Mittur , Nakul Pratap Saraiya
发明人： Daniel H. Bax , William Jackson Bibb, JR. , Russell M. Clapp , Tom Gourley , Geoffrey H. Hanson , Allen Hirashiki , Thomas Dean Lovett , Sharad Mehrotra , Shyam Mittur , Nakul Pratap Saraiya
IPC分类号： G06F3/00
CPC分类号： G06F9/4401 , G06F9/4405 , G06F9/4408 , H04L49/356
摘要： A Cost-Reduced Enterprise Server (CRES) system includes a flexible resource-efficient server having a plurality of Processor Memory Boards (PMBs) coupled to an Input/Output Module (IOM). The IOM provides all networking and storage interfaces for the server. The IOM is implemented as a field-replaceable pluggable module, and thus all Input/Output (I/O) capabilities or resources of a CRES system may be upgraded via replacement of the IOM. Each PMB is dividable into a pair of Symmetric MultiProcessor (SMP) complexes, and each complex is coupled to a respective portion of the I/O resources provided by the IOM. Each portion of the IOM provides a pair of I/O daughter-module connectors compatible with standard I/O interfaces, such as Peripheral Component Interconnect (PCI)-X and PCI-Express. One or more CRES systems may be coupled to one or more Enterprise Server (ES) systems to form a multi-chassis server managed collectively as one or more provisioned servers.
摘要翻译：降低成本的企业服务器（CRES）系统包括具有耦合到输入/输出模块（IOM）的多个处理器存储器板（PMB）的灵活的资源有效率的服务器。 IOM为服务器提供所有网络和存储接口。 IOM实现为现场可更换的可插拔模块，因此可以通过更换IOM来升级CRES系统的所有输入/输出（I / O）功能或资源。每个PMB可分为一对对称多处理器（SMP）复合体，每个复合体耦合到由IOM提供的I / O资源的相应部分。 IOM的每个部分都提供了一对与标准I / O接口兼容的I / O子模块连接器，如外设组件互连（PCI）-X和PCI-Express。一个或多个CRES系统可以耦合到一个或多个企业服务器（ES）系统，以形成作为一个或多个配置服务器集中管理的多机箱服务器。

2. 发明授权

US07861126B2 Implementation-efficient multiple-counter value hardware performance counter 有权
标题翻译：实现高效的多计数器硬件性能计数器
公开(公告)号：US07861126B2
公开(公告)日：2010-12-28
申请号：US12164094
申请日：2008-06-29
申请人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
发明人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.
摘要翻译：公开了一种实现高效的多计数器硬件性能计数器。一个实施例的硬件计数器包括存储器阵列和硬件递增器。阵列存储可由至少基于计数器值对应的事件数构成的索引可索引的计数器值。索引可以被构造为二进制数表示事件数量的位数的连接，以及二进制表示事件的限定符的数目的位数。增量器从数组中读取计数器值，增加计数器值，并将生成的计数器值写入数组。阵列可以被划分为存储有计数器值的存储体，其中每个存储体具有加法器的单独实例。每个银行可能有一个单独的索引实例，仅索引存储在银行中的那些计数器。

3. 发明授权

US07272754B2 Implementation-efficient multiple-counter value hardware performance counter 有权
公开(公告)号：US07272754B2
公开(公告)日：2007-09-18
申请号：US10672758
申请日：2003-09-27
申请人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
发明人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.

4. 发明申请

US20080263263A1 Implementation-efficient multiple-counter value hardware performance counter 有权
公开(公告)号：US20080263263A1
公开(公告)日：2008-10-23
申请号：US12164094
申请日：2008-06-29
申请人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
发明人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
IPC分类号： G06F12/00
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.

5. 发明授权

US08713295B2 Fabric-backplane enterprise servers with pluggable I/O sub-system 有权
标题翻译：具有可插拔I / O子系统的布线背板企业服务器
公开(公告)号：US08713295B2
公开(公告)日：2014-04-29
申请号：US11736355
申请日：2007-04-17
申请人： Daniel H. Bax , William Jackson Bibb, Jr. , Russell M. Clapp , Tom Gourley , Geoffrey H. Hanson , Allen Hirashiki , Thomas Dean Lovett , Sharad Mehrotra , Shyam Mittur , Nakul Pratap Saraiya
发明人： Daniel H. Bax , William Jackson Bibb, Jr. , Russell M. Clapp , Tom Gourley , Geoffrey H. Hanson , Allen Hirashiki , Thomas Dean Lovett , Sharad Mehrotra , Shyam Mittur , Nakul Pratap Saraiya
IPC分类号： G06F9/24 , G06F9/44
CPC分类号： G06F9/4401 , G06F9/4405 , G06F9/4408 , H04L49/356
摘要： A Cost-Reduced Enterprise Server (CRES) system includes a flexible resource-efficient server having a plurality of Processor Memory Boards (PMBs) coupled to an Input/Output Module (IOM). The IOM provides all networking and storage interfaces for the server. The IOM is implemented as a field-replaceable pluggable module, and thus all Input/Output (I/O) capabilities or resources of a CRES system may be upgraded via replacement of the IOM. Each PMB is dividable into a pair of Symmetric MultiProcessor (SMP) complexes, and each complex is coupled to a respective portion of the I/O resources provided by the IOM. Each portion of the IOM provides a pair of I/O daughter-module connectors compatible with standard I/O interfaces, such as Peripheral Component Interconnect (PCI)-X and PCI-Express. One or more CRES systems may be coupled to one or more Enterprise Server (ES) systems to form a multi-chassis server managed collectively as one or more provisioned servers.
摘要翻译：降低成本的企业服务器（CRES）系统包括具有耦合到输入/输出模块（IOM）的多个处理器存储器板（PMB）的灵活的资源有效率的服务器。 IOM为服务器提供所有网络和存储接口。 IOM实现为现场可更换的可插拔模块，因此可以通过更换IOM来升级CRES系统的所有输入/输出（I / O）功能或资源。每个PMB可分为一对对称多处理器（SMP）复合体，每个复合体耦合到由IOM提供的I / O资源的相应部分。 IOM的每个部分都提供了一对与标准I / O接口兼容的I / O子模块连接器，如外设组件互连（PCI）-X和PCI-Express。一个或多个CRES系统可以耦合到一个或多个企业服务器（ES）系统，以形成作为一个或多个配置服务器集中管理的多机箱服务器。

6. 发明授权

US07437622B2 Implementation-efficient multiple-counter value hardware performance counter 失效
标题翻译：实现高效的多计数器硬件性能计数器
公开(公告)号：US07437622B2
公开(公告)日：2008-10-14
申请号：US11738497
申请日：2007-04-22
申请人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
发明人： Carl E. Love , Donald R. DeSota , Jaeheon Jeong , Russell M. Clapp
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.
摘要翻译：公开了一种实现高效的多计数器硬件性能计数器。一个实施例的硬件计数器包括存储器阵列和硬件递增器。阵列存储可由至少基于计数器值对应的事件数构成的索引可索引的计数器值。索引可以被构造为二进制数表示事件数量的位数的连接，以及二进制表示事件的限定符的数目的位数。增量器从数组中读取计数器值，增加计数器值，并将生成的计数器值写入数组。阵列可以被划分为存储有计数器值的存储体，其中每个存储体具有加法器的单独实例。每个银行可能有一个单独的索引实例，仅索引存储在银行中的那些计数器。

7. 发明授权

US06848026B2 Caching memory contents into cache partitions based on memory locations 失效
标题翻译：基于内存位置将内存缓存缓存分区缓存
公开(公告)号：US06848026B2
公开(公告)日：2005-01-25
申请号：US10010788
申请日：2001-11-09
申请人： Donald R. DeSota , Adrian C. Moga , Carl E. Love , Russell M. Clapp
发明人： Donald R. DeSota , Adrian C. Moga , Carl E. Love , Russell M. Clapp
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0864 , G06F12/0848
摘要： Caching memory contents into cache partitions based on their locations is disclosed. A location of a line of memory to be cached in a cache is determined. The cache is partitioned into a number of cache sections. The section for the line of memory is determined based on the location of the line of memory as applied against a memory line location-dependent allocation policy. The line of memory is then stored in the section of the cache determined.
摘要翻译：公开了将存储器内容基于其位置缓存到高速缓存分区中。确定要缓存在高速缓存中的一行内存的位置。缓存被分割成多个高速缓存部分。存储器行的部分基于针对存储器线路位置相关分配策略应用的存储器行的位置来确定。然后将存储器行存储在所确定的缓存部分中。

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