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1. 发明申请

US20100283029A1 Programmable resistance memory and method of making same 审中-公开
标题翻译：可编程电阻记忆及其制作方法
公开(公告)号：US20100283029A1
公开(公告)日：2010-11-11
申请号：US12454002
申请日：2009-05-11
申请人： Charles Dennison , Wolodymyr Czubatyj , Jeff Fournier , Tom Latowski , James Reed , Regino Sandoval
发明人： Charles Dennison , Wolodymyr Czubatyj , Jeff Fournier , Tom Latowski , James Reed , Regino Sandoval
IPC分类号： H01L45/00 , H01L21/06 , H01L21/20
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/144 , H01L45/1608 , H01L45/1683
摘要： A memory includes multiple layers of deposited memory material. An etch is performed on at least one layer of deposited memory material prior to the deposition of a subsequent layer of memory material.
摘要翻译：存储器包括多层沉积的存储器材料。在沉积后续存储材料层之前，在至少一层沉积的存储材料上进行蚀刻。

2. 发明申请

US20080064200A1 Method to manufacture a phase change memory 有权
标题翻译：制造相变存储器的方法
公开(公告)号：US20080064200A1
公开(公告)日：2008-03-13
申请号：US11983188
申请日：2007-11-07
申请人： Brian Johnson , Charles Dennison
发明人： Brian Johnson , Charles Dennison
IPC分类号： H01L21/44
CPC分类号： G06F21/125 , G06F21/10 , H01L45/06 , H01L45/122 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/1666
摘要： Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.
摘要翻译：简而言之，根据本发明的实施例，提供了制造相变存储器的方法。该方法可以包括形成接触相变材料的侧壁表面和底表面的第一电极。该方法还可以包括形成接触相变材料的顶表面的第二电极。

3. 发明申请

US20080020508A1 Reducing oxidation of phase change memory electrodes 有权
标题翻译：减少相变记忆电极的氧化
公开(公告)号：US20080020508A1
公开(公告)日：2008-01-24
申请号：US11904557
申请日：2007-09-27
申请人： Charles Dennison
发明人： Charles Dennison
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2427 , H01L45/1233 , H01L45/141 , H01L45/1675
摘要： A phase change memory may be formed in a way which reduces oxygen infiltration through a chalcogenide layer overlying a lower electrode. Such infiltration may cause oxidation of the lower electrode which adversely affects performance. In one such embodiment, an etch through an overlying upper electrode layer may be stopped before reaching a layer which overlies said chalcogenide layer. Then, photoresist used for such etching may be utilized in a high temperature oxygen plasma. Only after such plasma treatment has been completed is that overlying layer removed, which ultimately exposes the chalcogenide.
摘要翻译：相变存储器可以以减少氧气穿过覆盖在下电极上的硫属化物层的方式形成。这种渗透可能导致下部电极的氧化，这对性能有不利影响。在一个这样的实施例中，通过覆盖的上电极层的蚀刻可以在到达覆盖所述硫族化物层的层之前停止。然后，可以在高温氧等离子体中使用用于这种蚀刻的光致抗蚀剂。只有在这样的等离子体处理完成之后，去除了上层，最终暴露了硫族化物。

4. 发明申请

US20070138467A1 Forming phase change memories 有权
标题翻译：形成相变记忆
公开(公告)号：US20070138467A1
公开(公告)日：2007-06-21
申请号：US11706000
申请日：2007-02-13
申请人： Chien Chiang , Charles Dennison , Tyler Lowrey
发明人： Chien Chiang , Charles Dennison , Tyler Lowrey
IPC分类号： H01L31/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.
摘要翻译：在一些情况下，通过将相变材料层形成为平面构型，相变存储器可以表现出改善的性能和较低的成本。可以在相变材料层的下方设置加热器，以适当地加热材料以引起相变。加热器可以耦合到适当的导体。

5. 发明申请

US20060234469A1 A method of forming semiconductor structures 审中-公开
标题翻译：一种形成半导体结构的方法
公开(公告)号：US20060234469A1
公开(公告)日：2006-10-19
申请号：US11409134
申请日：2006-04-21
申请人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
发明人： David Dickerson , Richard Lane , Charles Dennison , Kunal Parekh , Mark Fischer , John Zahurak
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

6. 发明授权

US07005666B2 Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby 有权
标题翻译：选择性地增加相变存储器单元中的下编程电极的顶电阻和由此获得的结构的方法
公开(公告)号：US07005666B2
公开(公告)日：2006-02-28
申请号：US10679637
申请日：2003-10-06
申请人： Charles Dennison
发明人： Charles Dennison
IPC分类号： H01L47/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/52 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： The present invention relates to a process of forming a phase-change memory. A lower electrode is disposed in a first dielectric film. The lower electrode comprises an upper section and a lower section. The upper section extends beyond the first dielectric film. Resistivity in the upper section is higher than in the lower section. A second dielectric film is disposed over the first dielectric film and has an upper surface that is coplanar with the upper section at an upper surface.
摘要翻译：本发明涉及一种形成相变存储器的方法。下电极设置在第一电介质膜中。下部电极包括上部和下部。上部延伸超过第一介电膜。上段电阻率高于下段。第二电介质膜设置在第一电介质膜的上方，并且在上表面具有与上部共面的上表面。

7. 发明申请

US20050142703A1 Dual-gate transistor device and method of forming a dual-gate transistor device 有权
标题翻译：双栅极晶体管器件和形成双栅极晶体管器件的方法
公开(公告)号：US20050142703A1
公开(公告)日：2005-06-30
申请号：US10932192
申请日：2004-09-01
申请人： John Zahurak , Brent Keeth , Charles Dennison
发明人： John Zahurak , Brent Keeth , Charles Dennison
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/00 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/66772 , H01L21/76897 , H01L21/76898 , H01L21/84 , H01L27/1203 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.
摘要翻译：根据本发明的实施例提供了形成双门限半导体绝缘体（SOI）器件的方法。这样的方法包括形成与SOI衬底的半导体层的第一侧可操作地相邻的第一晶体管结构。绝缘体层材料从第一晶体管结构的源极/漏极接触结构和第二晶体管结构之间的半导体层的第二侧被去除，第二晶体管结构可操作地邻近半导体层的第二侧并与第一晶体管结构对准。

8. 发明授权

US06593176B2 METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT 有权
标题翻译：用于形成用于创建用于两个存储器阵列元件和一个双极接触器的个人活动区域的单个更改存储器双极阵列的方法
公开(公告)号：US06593176B2
公开(公告)日：2003-07-15
申请号：US10196870
申请日：2002-07-15
申请人： Charles Dennison
发明人： Charles Dennison
IPC分类号： H01L218238
CPC分类号： H01L29/685 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： The invention relates to a process of forming a phase-change memory device. The process includes forming a salicide structure in peripheral logic portion of the substrate and preventing forming salicide structures in the memory array. The device may include a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode.
摘要翻译：本发明涉及一种形成相变存储器件的方法。该方法包括在衬底的外围逻辑部分中形成硅化物结构，并防止在存储器阵列中形成自对准硅化物结构。该器件可以包括双宽沟槽，其中沉积单个膜，但是从其形成两个隔离的下电极。此外，形成与下电极连通的二极管叠层。

9. 发明授权

US6046472A Graded LDD implant process for sub-half-micron MOS devices 失效
公开(公告)号：US6046472A
公开(公告)日：2000-04-04
申请号：US949997
申请日：1997-10-14
申请人： Aftab Ahmad , Charles Dennison
发明人： Aftab Ahmad , Charles Dennison
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/784
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/823814 , H01L29/1083 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90 , Y10S257/917
摘要： A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

10. 发明授权

US5705838A Array of bit line over capacitor array of memory cells 失效
标题翻译：存储单元电容阵列上的位线阵列
公开(公告)号：US5705838A
公开(公告)日：1998-01-06
申请号：US692748
申请日：1996-08-06
申请人： Mark Jost , Charles Dennison
发明人： Mark Jost , Charles Dennison
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/41
CPC分类号： H01L27/10852 , H01L21/768 , H01L21/76877 , H01L27/10808 , H01L28/40 , H01L28/60 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , Y10S148/05
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; the capacitor comprising an inner storage node, a capacitor dielectric layer, and an outer cell node; the inner storage node electrically connecting with the one active area, the inner storage node having an upper surface at an elevation; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the other active area; and g) an electrically conductive bit line plug extending through the insulating layer to contact with the other active area and electrically interconnect the bit line with the other active area, the bit line plug being homogeneous in composition between the other active area and the elevation of the inner storage node upper surface. A method of producing such a construction is also disclosed.
摘要翻译：半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; 所述电容器包括内部存储节点，电容器介电层和外部单元节点; 所述内部存储节点与所述一个活动区域电连接，所述内部存储节点具有在高度处的上表面; e）有点线 f）位于位线和另一个有效区域之间的介电绝缘层; 并且g）导电位线插头，其延伸穿过所述绝缘层以与所述另一有源区域接触并且将所述位线与所述另一个有源区域电互连，所述位线插头在所述另一个有效区域和内部存储节点上表面。还公开了一种制造这种结构的方法。

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