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1. 发明授权

US08929118B2 Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line 有权
标题翻译：具有芯片间连接单元的堆叠存储器件，包括其的存储器系统以及补偿传输线路的延迟时间的方法
公开(公告)号：US08929118B2
公开(公告)日：2015-01-06
申请号：US13080061
申请日：2011-04-05
申请人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
发明人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
IPC分类号： G11C5/06 , G11C5/02 , G11C7/10
CPC分类号： G11C7/10 , G11C5/02 , G11C7/1048
摘要： A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.
摘要翻译：提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号传输线。层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

2. 发明申请

US20140346516A1 SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR PACKAGES 审中-公开
标题翻译：半导体存储器件和半导体封装
公开(公告)号：US20140346516A1
公开(公告)日：2014-11-27
申请号：US14450359
申请日：2014-08-04
申请人： Ho-Cheol LEE , Chi-Sung OH , Jin-Kuk KIM
发明人： Ho-Cheol LEE , Chi-Sung OH , Jin-Kuk KIM
IPC分类号： H01L25/065 , H01L21/66 , H01L27/02 , H01L23/00 , H01L27/108
CPC分类号： H01L25/0657 , G11C5/025 , G11C5/06 , H01L22/32 , H01L24/09 , H01L24/73 , H01L27/0255 , H01L27/108 , H01L2224/0401 , H01L2224/0912 , H01L2224/09179 , H01L2224/09515 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/06541 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.
摘要翻译：半导体存储器件包括半导体管芯和输入 - 输出凸块焊盘部分。半导体管芯包括多个存储单元阵列。输入输出凸块焊盘部分形成在半导体管芯的中心区域。输入 - 输出凸块焊盘部件提供多个通道，用于将每个存储单元阵列独立地连接到外部设备。半导体存储器件可以采用多通道接口，从而具有相对较低功耗的高性能。

3. 发明授权

US08796863B2 Semiconductor memory devices and semiconductor packages 有权
标题翻译：半导体存储器件和半导体封装
公开(公告)号：US08796863B2
公开(公告)日：2014-08-05
申请号：US12891141
申请日：2010-09-27
申请人： Ho-Cheol Lee , Chi-Sung Oh , Jin-Kuk Kim
发明人： Ho-Cheol Lee , Chi-Sung Oh , Jin-Kuk Kim
IPC分类号： H01L29/12 , H01L29/40
CPC分类号： H01L25/0657 , G11C5/025 , G11C5/06 , H01L22/32 , H01L24/09 , H01L24/73 , H01L27/0255 , H01L27/108 , H01L2224/0401 , H01L2224/0912 , H01L2224/09179 , H01L2224/09515 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32225 , H01L2224/48227 , H01L2224/73207 , H01L2224/73265 , H01L2225/06541 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.
摘要翻译：半导体存储器件包括半导体管芯和输入 - 输出凸块焊盘部分。半导体管芯包括多个存储单元阵列。输入输出凸块焊盘部分形成在半导体管芯的中心区域。输入 - 输出凸块焊盘部件提供多个通道，用于将每个存储单元阵列独立地连接到外部设备。半导体存储器件可以采用多通道接口，从而具有相对较低功耗的高性能。

4. 发明授权

US08396682B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08396682B2
公开(公告)日：2013-03-12
申请号：US12900547
申请日：2010-10-08
申请人： Chi-Sung Oh , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
发明人： Chi-Sung Oh , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
IPC分类号： G01R27/28 , G06F19/00
CPC分类号： G01R31/2884 , G01R31/31726
摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.
摘要翻译：提供半导体器件。半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

5. 发明申请

US20120272112A1 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES 有权
标题翻译：半导体器件和半导体封装
公开(公告)号：US20120272112A1
公开(公告)日：2012-10-25
申请号：US13453447
申请日：2012-04-23
申请人： Chi-sung OH , Jung-sik KIM , Ho-cheol LEE , Jung-bae LEE
发明人： Chi-sung OH , Jung-sik KIM , Ho-cheol LEE , Jung-bae LEE
IPC分类号： G01R31/3177 , H01L23/485 , G06F11/25
CPC分类号： G01R31/318555 , G01R31/318538 , G01R31/318597 , G01R31/3187 , H01L22/32 , H01L23/481 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13541 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2224/81193 , H01L2924/12042 , H01L2924/15192 , H01L2924/014 , H01L2924/00014 , H01L2924/00 , H01L2924/206
摘要： Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.
摘要翻译：半导体器件被配置为测试包括一个或多个微凸块的微凸块和边界扫描测试块的连接性，用于通过扫描输入到微凸块的数据并输出扫描数据来测试微凸块的连接性。半导体器件可以包括第一芯片，其包括焊球和与各个焊球电耦合的至少一个或多个开关，以及堆叠在第一芯片的顶部上并与直流存取模式的开关电耦合的第二芯片，包括微从焊球传出的输入/输出信号的凸起。

6. 发明授权

US08166238B2 Method, device, and system for preventing refresh starvation in shared memory bank 有权
标题翻译：用于防止共享存储器中刷新不足的方法，设备和系统
公开(公告)号：US08166238B2
公开(公告)日：2012-04-24
申请号：US11977047
申请日：2007-10-23
申请人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C7/1075 , G11C11/40603 , G11C11/40618
摘要： A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.
摘要翻译：多端口存储器件包括刷新寄存器和刷新控制器，用于防止存储器件的共享存储器单元中的刷新不足。存储装置还包括共享对共享存储器单元的访问的多个端口。刷新寄存器存储关于至少一个刷新命令的信息。刷新控制器根据存储在刷新寄存器中的信息来确定是否在端口权限转换时激活内部刷新操作。

7. 发明申请

US20120002456A1 METHOD OF ARRANGING PADS IN SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE USING THE METHOD, AND PROCESSING SYSTEM HAVING MOUNTED THEREIN THE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：在半导体器件中安装衬垫的方法，使用该方法的半导体存储器件和具有安装在半导体存储器件上的处理系统
公开(公告)号：US20120002456A1
公开(公告)日：2012-01-05
申请号：US13174824
申请日：2011-07-01
申请人： Chi-sung OH
发明人： Chi-sung OH
IPC分类号： G11C5/06 , H01L23/58 , G06F17/50
CPC分类号： G06F17/5072 , G06F2217/40 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.
摘要翻译：一种在半导体存储器件中布置焊盘的方法，使用该方法的半导体存储器件以及其中安装有半导体存储器件的处理系统。该方法包括将设置在半导体存储器件的存储器芯片中的焊盘分成用于在晶片上进行存储芯片测试的监控焊盘，配置用于封装中的线连接的封装焊盘以及配置用于存储器芯片测试的公共焊盘封装中的晶片和导线连接，并将监测焊盘和封装焊盘分别布置在存储器芯片上的列中。

8. 发明申请

US20110035544A1 MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING MAILBOX AREAS AND MAILBOX ACCESS CONTROL METHOD THEREOF 失效
标题翻译：具有邮箱区域和邮箱访问控制方法的多通道可访问半导体存储器件
公开(公告)号：US20110035544A1
公开(公告)日：2011-02-10
申请号：US12909069
申请日：2010-10-21
申请人： Chi-Sung OH , Yong-Jun KIM , Kyung-Woo NAM , Jin-Kuk KIM , Soo-Young KIM
发明人： Chi-Sung OH , Yong-Jun KIM , Kyung-Woo NAM , Jin-Kuk KIM , Soo-Young KIM
IPC分类号： G06F12/06 , G06F12/00
CPC分类号： G11C5/02 , G11C8/12
摘要： A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.
摘要翻译：提供具有邮箱区域和邮箱访问控制方法的多路径可访问半导体存储装置。半导体存储器件包括N个端口，分配在存储单元阵列中的至少一个共享存储区域和N个用于消息通信的邮箱区域。所述至少一个共享存储区域可操作地连接到所述N个端口，并且可通过多个数据输入/输出线路访问，以在所述至少一个共享存储区域和一个端口之间形成数据访问路径，在N个端口中的至少一个存储区域的权限。 N个邮箱区域与N个端口一一对应地提供，并且当应用至少一个共享存储区域的预定区域的地址时可以通过多个数据输入/输出线路访问邮箱区域到半导体存储器件。可以获得邮箱的有效布局和高效的邮件访问路径。

9. 发明授权

US08680524B2 Method of arranging pads in semiconductor device, semiconductor memory device using the method, and processing system having mounted therein the semiconductor memory device 有权
标题翻译：在半导体器件中布置焊盘的方法，使用该方法的半导体存储器件以及其中安装有半导体存储器件的处理系统
公开(公告)号：US08680524B2
公开(公告)日：2014-03-25
申请号：US13174824
申请日：2011-07-01
申请人： Chi-sung Oh
发明人： Chi-sung Oh
IPC分类号： H01L29/04 , G01R27/28
CPC分类号： G06F17/5072 , G06F2217/40 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.
摘要翻译：一种在半导体存储器件中布置焊盘的方法，使用该方法的半导体存储器件以及其中安装有半导体存储器件的处理系统。该方法包括将设置在半导体存储器件的存储器芯片中的焊盘分成用于在晶片上进行存储芯片测试的监控焊盘，配置用于封装中的线连接的封装焊盘以及配置用于存储器芯片测试的公共焊盘封装中的晶片和导线连接，并将监测焊盘和封装焊盘分别布置在存储器芯片上的列中。

10. 发明授权

US08456881B2 Stacked memory and devices including the same 有权
标题翻译：堆叠的内存和设备包括相同
公开(公告)号：US08456881B2
公开(公告)日：2013-06-04
申请号：US13007716
申请日：2011-01-17
申请人： Chi Sung Oh
发明人： Chi Sung Oh
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , H01L24/16 , H01L25/0657 , H01L2924/14 , H01L2924/00
摘要： In one embodiment, the stacked memory includes a first group of stacked memory chips, a second group of stacked memory chips, and connection terminals configured to electrically connect a first memory chip among the stacked memory chips in the first group to a second memory chip among the stacked memory chips in the second group.
摘要翻译：在一个实施例中，堆叠存储器包括第一组堆叠存储器芯片，第二组堆叠存储器芯片，以及连接端子，其被配置为将第一组中的堆叠存储器芯片中的第一存储器芯片电连接到第一存储器芯片中的第二存储器芯片，第二组中堆叠的存储器芯片。

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