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1. 发明授权

US09153506B2 System and method for through silicon via yield 有权
标题翻译：通过硅产量的系统和方法
公开(公告)号：US09153506B2
公开(公告)日：2015-10-06
申请号：US13542896
申请日：2012-07-06
申请人： Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
发明人： Chien Rhone Wang , Kewei Zuo , Chen-Hua Yu , Jing-Cheng Lin , Yen-Hsin Liu
IPC分类号： G06F19/00 , H01L21/66 , H01L21/768
CPC分类号： H01L22/20 , H01L21/76898 , H01L22/12
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) fabrication method to form an IC structure having one or more through silicon via (TSV) features. The IC fabrication method includes performing a plurality of processing steps; collecting physical metrology data from the plurality of processing steps; collecting virtual metrology data from the plurality of processing steps based on the physical metrology data; generating a yield prediction to the IC structure based on the physical metrology data and the virtual metrology data; and identifying an action at an earlier processing step based on the yield prediction.
摘要翻译：本公开提供了用于形成具有一个或多个贯穿硅通孔（TSV）特征的IC结构的集成电路（IC）制造方法的一个实施例。 IC制作方法包括执行多个处理步骤; 从多个处理步骤收集物理计量数据; 基于所述物理测量数据从所述多个处理步骤收集虚拟测量数据; 基于物理测量数据和虚拟测量数据，为IC结构生成产量预测; 以及基于所述产量预测在较早的处理步骤中识别动作。

2. 发明申请

US20130024019A1 APPARATUS AND METHODS FOR END POINT DETERMINATION IN SEMICONDUCTOR PROCESSING 审中-公开
标题翻译：用于半导体处理中端点测定的装置和方法
公开(公告)号：US20130024019A1
公开(公告)日：2013-01-24
申请号：US13285679
申请日：2011-10-31
申请人： Chien Rhone Wang , Tzu-Cheng Lin , Yu-Jen Cheng , Chih-Wei Lai , Hung-Pin Chang , Tsang-Jiuh Wu
发明人： Chien Rhone Wang , Tzu-Cheng Lin , Yu-Jen Cheng , Chih-Wei Lai , Hung-Pin Chang , Tsang-Jiuh Wu
IPC分类号： G05B13/04
CPC分类号： G05B19/41875 , G05B2219/32201 , G05B2219/32205 , G05B2219/45031 , Y02P90/20 , Y02P90/22
摘要： Methods and apparatus for performing end point determination are disclosed. An embodiment includes an apparatus comprising a process tool and a programmable processor. The process tool has an output for signaling in-situ measurements of physical parameters during processing of a wafer in the process tool, and the process tool has an input for receiving a signal indicating a modification of a recipe for the processing. The programmable processor is for executing a virtual metrology model of the process tool to estimate an estimated characteristic of the wafer achieved during the processing. The estimated characteristic is based on the in-situ measurements and the virtual metrology model. The programmable processor has an output for transmitting the signal when the estimated characteristic exceeds a predetermined threshold based on a target characteristic.
摘要翻译：公开了用于执行终点确定的方法和装置。实施例包括一种包括处理工具和可编程处理器的装置。处理工具具有用于在处理工具中的晶片处理期间信号化物理参数的原位测量的输出，并且处理工具具有用于接收指示用于处理的配方的修改的信号的输入。可编程处理器用于执行处理工具的虚拟计量模型以估计在处理期间实现的晶片的估计特性。估计的特征是基于原位测量和虚拟计量模型。可编程处理器具有用于当估计特性基于目标特性超过预定阈值时发送信号的输出。

3. 发明授权

US5171412A Material deposition method for integrated circuit manufacturing 失效
标题翻译：集成电路制造的材料沉积方法
公开(公告)号：US5171412A
公开(公告)日：1992-12-15
申请号：US749096
申请日：1991-08-23
申请人： Homoyoun Talieh , Avi Tepman , Hoa Thi Kieu , Chien-Rhone Wang
发明人： Homoyoun Talieh , Avi Tepman , Hoa Thi Kieu , Chien-Rhone Wang
IPC分类号： C23C14/04 , C23C14/22 , C23C14/34 , C23C14/54 , C23C14/58 , C23C28/00 , H01L21/203 , H01L21/28 , H01L21/285 , H01L21/321 , H01L21/768
CPC分类号： C23C14/046 , C23C14/34 , H01L21/2855 , H01L21/321 , H01L21/76877
摘要： The improved material deposition process of the present invention utilizes a first, low temperature deposition step followed by a second, high temperature/high power deposition step. In the first deposition step a collimation plate is placed between the sputtering target and the substrate, such that a collimated stream of sputtered material is deposited upon the substrate. The collimated stream provides a seed layer which aids in eliminating voids by partially filling the holes and grooves in the surface of the substrate. The second deposition step is conducted as a high temperature sputtering deposition. At the high temperature the sputtered material joins and flows with the seed layer, whereby the holes and grooves are more easily filled without voids and an improved planarized layer is achieved.

4. 发明授权

US09010617B2 Solder joint reflow process for reducing packaging failure rate 有权
标题翻译：焊接回流工艺，降低包装故障率
公开(公告)号：US09010617B2
公开(公告)日：2015-04-21
申请号：US12987702
申请日：2011-01-10
申请人： Chen-Hua Yu , Wen-Yao Chang , Chien Rhone Wang , Kewei Zuo , Chung-Shi Liu
发明人： Chen-Hua Yu , Wen-Yao Chang , Chien Rhone Wang , Kewei Zuo , Chung-Shi Liu
IPC分类号： B23K31/02 , H01L21/44 , H01L23/00
CPC分类号： H01L24/81 , H01L24/13 , H01L24/75 , H01L2224/13111 , H01L2224/16145 , H01L2224/16225 , H01L2224/7525 , H01L2224/75251 , H01L2224/75252 , H01L2224/75283 , H01L2224/75501 , H01L2224/75502 , H01L2224/81055 , H01L2224/81097 , H01L2224/81098 , H01L2224/8121 , H01L2224/8123 , H01L2224/81805 , H01L2224/8181 , H01L2224/81815 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2224/13139
摘要： In a reflow process, a plurality of solder bumps between a first workpiece and a second workpiece is melted. During a solidification stage of the plurality of solder bumps, the plurality of solder bumps is cooled at a first cooling rate. After the solidification stage is finished, the plurality of solder bumps is cooled at a second cooling rate lower than the first cooling rate.
摘要翻译：在回流工艺中，第一工件和第二工件之间的多个焊料凸块熔化。在多个焊料凸块的凝固阶段期间，以第一冷却速度冷却多个焊料凸块。凝固阶段结束后，以比第一冷却速度低的第二冷却速度冷却多个焊锡凸块。

5. 发明授权

US08791579B2 Adjusting sizes of connectors of package components 有权
标题翻译：调整包装组件连接器的尺寸
公开(公告)号：US08791579B2
公开(公告)日：2014-07-29
申请号：US13299100
申请日：2011-11-17
申请人： Chih-Wei Lai , Ming-Che Ho , Tzong-Hann Yang , Chien Rhone Wang , Chia-Tung Chang , Hung-Jui Kuo , Chung-Shi Liu
发明人： Chih-Wei Lai , Ming-Che Ho , Tzong-Hann Yang , Chien Rhone Wang , Chia-Tung Chang , Hung-Jui Kuo , Chung-Shi Liu
IPC分类号： H01L23/52 , H01L23/48 , H01L23/485 , H01L23/495
CPC分类号： G06F17/5077 , G06F17/5072 , H01L23/488 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05016 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05552 , H01L2224/05572 , H01L2224/05666 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/13006 , H01L2224/13012 , H01L2224/13014 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1403 , H01L2224/14132 , H01L2924/00014 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029
摘要： A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.
摘要翻译：一种装置包括在包装部件的顶表面上的多个连接器。多个连接器包括具有第一横向尺寸的第一连接器和具有第二横向尺寸的第二连接器。第二横向尺寸大于第一横向尺寸。第一和第二横向尺寸在平行于包装部件的主表面的方向上测量。

6. 发明申请

US20130244346A1 Packaging Methods, Material Dispensing Methods and Apparatuses, and Automated Measurement Systems 有权
标题翻译：包装方法，材料分配方法和装置以及自动测量系统
公开(公告)号：US20130244346A1
公开(公告)日：2013-09-19
申请号：US13420383
申请日：2012-03-14
申请人： Chien Rhone Wang , Chih-Wei Lai , Chih-Chiang Chang , Kewei Zuo , Jing-Cheng Lin
发明人： Chien Rhone Wang , Chih-Wei Lai , Chih-Chiang Chang , Kewei Zuo , Jing-Cheng Lin
IPC分类号： H01L21/66 , G06F17/00
CPC分类号： G06F17/00 , H01L22/12 , H01L22/20 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/83951 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/181 , H01L2224/81 , H01L2924/00012 , H01L2924/00
摘要： Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.
摘要翻译：公开了包装方法，材料分配方法和装置以及自动测量系统。在一个实施例中，包装半导体器件的方法包括将第二管芯耦合到第一管芯的顶表面，在第一管芯和第二管芯之间分配第一量的底部填充材料，以及捕获底部填充材料的图像。基于所捕获的图像，在第一模具和第二模具之间分配第二量或不需要额外量的底部填充材料。

7. 发明授权

US5108570A Multistep sputtering process for forming aluminum layer over stepped semiconductor wafer 失效
标题翻译：用于在步进半导体膜上形成铝层的多层溅射工艺
公开(公告)号：US5108570A
公开(公告)日：1992-04-28
申请号：US502362
申请日：1990-03-30
申请人： Chien-Rhone Wang
发明人： Chien-Rhone Wang
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/76877
摘要： A multistep aluminum sputtering process is disclosed wherein aluminum is sputtered onto the surface of a semiconductor wafer and low areas between closely spaced apart raised portions on the wafer, such as closely spaced apart steps, narrow trenches, or small diameter vias, are completely fulled in by the sputtered aluminum. This results in the formation of an aluminum layer which is not thinned out in such low areas, and which has a surface which ranges from substantially planar to a positive slope, such as shown at 24' and 26' in FIG. 2. The first step is carried out by sputtering from about 200 to about 2000 Angstroms of aluminum while the wafer temperature is within a range of from about 50.degree. C. to about 250.degree. C. and the sputtering plasma is at a power of from about 1 to about 16 kilowatts. The power level range is then changed to from about 14 to about 20 kilowatts, a DC or AC bias is applied to the wafer, and aluminum is then sputtered either for an additional time period of about 20 to about 40 seconds or until the wafer temperature reaches 500.degree. C., whichever occurs first, in a second step. Then the back side of the wafer is contacted by a thermally conductive gas to control the wafer temperature while further aluminum is optionally sputtered onto the wafer for an additional 0 to 45 seconds in a third step.

8. 发明申请

US20130127059A1 Adjusting Sizes of Connectors of Package Components 有权
公开(公告)号：US20130127059A1
公开(公告)日：2013-05-23
申请号：US13299100
申请日：2011-11-17
申请人： Chih-Wei Lai , Ming-Che Ho , Tzong-Hann Yang , Chien Rhone Wang , Chia-Tung Chang , Hung-Jui Kuo , Chung-Shi Liu
发明人： Chih-Wei Lai , Ming-Che Ho , Tzong-Hann Yang , Chien Rhone Wang , Chia-Tung Chang , Hung-Jui Kuo , Chung-Shi Liu
IPC分类号： H01L23/48 , H01L21/66 , G06F17/50
CPC分类号： G06F17/5077 , G06F17/5072 , H01L23/488 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/034 , H01L2224/03912 , H01L2224/0401 , H01L2224/05016 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05552 , H01L2224/05572 , H01L2224/05666 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/13006 , H01L2224/13012 , H01L2224/13014 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1403 , H01L2224/14132 , H01L2924/00014 , H01L2924/00012 , H01L2924/01047 , H01L2924/01029
摘要： A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

9. 发明申请

US20130023065A1 Apparatus and Methods for End Point Determination in Reactive Ion Etching 有权
标题翻译：反应离子蚀刻中终点测定的装置和方法
公开(公告)号：US20130023065A1
公开(公告)日：2013-01-24
申请号：US13189287
申请日：2011-07-22
申请人： Chien Rhone Wang , Tzu-Cheng Lin , Yu-Jen Cheng , Chih-Wei Lai , Hung-Pin Chang , Tsang-Jiuh Wu
发明人： Chien Rhone Wang , Tzu-Cheng Lin , Yu-Jen Cheng , Chih-Wei Lai , Hung-Pin Chang , Tsang-Jiuh Wu
IPC分类号： H01L21/66
CPC分类号： H01J37/32963
摘要： Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.
摘要翻译：执行终点确定的方法和装置。一种方法包括将晶片接收到用于进行RIE蚀刻的蚀刻工具室中; 开始RIE蚀刻以在晶片中形成通孔; 接收与RIE蚀刻工艺相关的蚀刻工具室的一个或多个物理参数的原位测量; 为腔室中的RIE蚀刻提供虚拟计量模型; 将接收到的原位测量值输入到腔室中的RIE蚀刻的虚拟测量模型; 执行虚拟计量模型以通过深度估计电流; 将经过深度的估计电流与目标深度进行比较; 并且当比较指示当前经过深度在目标深度的预定阈值内时; 输出停止信号。公开了一种用于该方法实施例的装置。

10. 发明授权

US09390060B2 Packaging methods, material dispensing methods and apparatuses, and automated measurement systems 有权
标题翻译：包装方法，材料分配方法和装置以及自动测量系统
公开(公告)号：US09390060B2
公开(公告)日：2016-07-12
申请号：US13420383
申请日：2012-03-14
申请人： Chien Rhone Wang , Chih-Wei Lai , Chih-Chiang Chang , Kewei Zuo , Jing-Cheng Lin
发明人： Chien Rhone Wang , Chih-Wei Lai , Chih-Chiang Chang , Kewei Zuo , Jing-Cheng Lin
IPC分类号： H01L21/66 , G06F17/00 , H01L23/00 , H01L25/065
CPC分类号： G06F17/00 , H01L22/12 , H01L22/20 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/83951 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/181 , H01L2224/81 , H01L2924/00012 , H01L2924/00
摘要： Packaging methods, material dispensing methods and apparatuses, and automatic measurement systems are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a second die to a top surface of a first die, dispensing a first amount of underfill material between the first die and the second die, and capturing an image of the underfill material. Based on the image captured, a second amount or no additional amount of underfill material is dispensed between the first die and the second die.
摘要翻译：公开了包装方法，材料分配方法和装置以及自动测量系统。在一个实施例中，包装半导体器件的方法包括将第二管芯耦合到第一管芯的顶表面，在第一管芯和第二管芯之间分配第一量的底部填充材料，以及捕获底部填充材料的图像。基于所捕获的图像，在第一模具和第二模具之间分配第二量或不需要额外量的底部填充材料。

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